Hierarchical thread scheduling

ABSTRACT

Examples described herein relate to a graphics processing unit (GPU) coupled to the memory device, the GPU configured to: execute an instruction thread; determine if a dual directional signal barrier is associated with the instruction thread; and based on clearance of the dual directional signal barrier for a particular signal barrier identifier and a mode of operation, indicate a clearance of the dual directional signal barrier for the mode of operation, wherein the dual directional signal barrier is to provide a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.

RELATED APPLICATION

The present application is a continuation-in-part and claims the benefit of a priority date of U.S. patent application Ser. No. 16/892,202, filed Jun. 3, 2020 (AC7639-US), the entire disclosure of which is incorporated herein by reference.

RELATED ART

Hierarchical parallelism is a popular model for execution of applications on central processing units (CPUs). For example, OpenMP Application Programming Interface Versions 1.0 and onward support multi-platform shared-memory parallel programming in C, C++ and Fortran. OpenMP Application Programming Interface defines an interface for development of parallel applications on computing platforms. OpenMP provides for a lead thread to execute and then fork to multiple worker threads so that the threads then run concurrently in a computing environment. Various vendors such as IBM, Nvidia, and AMD support hierarchical parallelism by use of a software state machine.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a processing system according to an embodiment.

FIGS. 2A-2D illustrate computing systems and graphics processors provided by embodiments described herein.

FIGS. 3A-3C illustrate block diagrams of additional graphics processor and compute accelerator architectures provided by embodiments described herein.

FIG. 4 is a block diagram of a graphics processing engine of a graphics processor in accordance with some embodiments.

FIGS. 5A-5B illustrate thread execution logic including an array of processing elements employed in a graphics processor core according to embodiments described herein.

FIG. 6 illustrates an additional execution unit, according to an embodiment.

FIG. 7 is a block diagram illustrating a graphics processor instruction formats according to some embodiments.

FIG. 8 is a block diagram of another embodiment of a graphics processor.

FIG. 9A is a block diagram illustrating a graphics processor command format according to some embodiments.

FIG. 9B is a block diagram illustrating a graphics processor command sequence according to an embodiment.

FIG. 10 illustrates an exemplary graphics software architecture for a data processing system according to some embodiments.

FIG. 11A is a block diagram illustrating an IP core development system that may be used to manufacture an integrated circuit to perform operations according to an embodiment.

FIG. 11B illustrates a cross-section side view of an integrated circuit package assembly, according to some embodiments described herein.

FIG. 11C illustrates a package assembly that includes multiple units of hardware logic chiplets connected to a substrate.

FIG. 11D illustrates a package assembly including interchangeable chiplets, according to an embodiment.

FIGS. 12, 13A and 13B illustrate exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein.

FIG. 14 depicts an example of execution of multiple teams of threads.

FIG. 15 depicts an example of transition from a single leading thread to multiple worker threads.

FIG. 16 depicts an example of use of multiple barriers.

FIG. 17 depicts an example of use of a barrier gateway.

FIG. 18 depicts an example of multiple thread execution on a matrix of values that can utilize multiple signal barrier identifiers.

FIG. 19 depicts an example system.

FIG. 20 depicts an example process.

FIG. 21 depicts an example process.

FIG. 22 depicts an example sequence using a signal barrier.

FIG. 23 depicts an example sequence using a dual directional signal barrier.

FIG. 24 depicts an example process.

FIG. 25 depicts an example process.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. It will be apparent, however, to one skilled in the art that the embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of the embodiments of the invention.

Various embodiments provide for compiling a portion of a code segment that applies hierarchical parallelism and including one or more signal barriers with one or more signal barrier identifiers. In some embodiments, a signal barrier can identify whether a thread is a producer or consumer of data or both producer of data and consumer of data as well as number of producers or consumers. In some embodiments, the signal barrier can indicate a level of memory sharing among a producer thread and one or more waiting consumer threads. The signal barrier can indicate an instruction pointer location in an instruction queue to jump to after clearing of the signal barrier. In some embodiments, the signal barrier is dual directional and allows communication from producer to consumer or consumer to producer. Various embodiments can use a hardware implemented gateway to determine if a signal barrier associated with a particular signal barrier identifier is to be cleared for one or more threads and permit execution of such one or more threads.

System Overview

FIG. 1 is a block diagram of a processing system 100, according to an embodiment. System 100 may be used in a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 102 or processor cores 107. In one embodiment, the system 100 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices such as within Internet-of-things (IoT) devices with wired or wireless connectivity to a local or wide area network.

In one embodiment, system 100 can include, couple with, or be integrated within: a server-based gaming platform; a game console, including a game and media console; a mobile gaming console, a handheld game console, or an online game console. In some embodiments the system 100 is part of a mobile phone, smart phone, tablet computing device or mobile Internet-connected device such as a laptop with low internal storage capacity. Processing system 100 can also include, couple with, or be integrated within: a wearable device, such as a smart watch wearable device; smart eyewear or clothing enhanced with augmented reality (AR) or virtual reality (VR) features to provide visual, audio or tactile outputs to supplement real world visual, audio or tactile experiences or otherwise provide text, audio, graphics, video, holographic images or video, or tactile feedback; other augmented reality (AR) device; or other virtual reality (VR) device. In some embodiments, the processing system 100 includes or is part of a television or set top box device. In one embodiment, system 100 can include, couple with, or be integrated within a self-driving vehicle such as a bus, tractor trailer, car, motor or electric power cycle, plane or glider (or any combination thereof). The self-driving vehicle may use system 100 to process the environment sensed around the vehicle.

In some embodiments, the one or more processors 102 each include one or more processor cores 107 to process instructions which, when executed, perform operations for system or user software. In some embodiments, at least one of the one or more processor cores 107 is configured to process a specific instruction set 109. In some embodiments, instruction set 109 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). One or more processor cores 107 may process a different instruction set 109, which may include instructions to facilitate the emulation of other instruction sets. Processor core 107 may also include other processing devices, such as a Digital Signal Processor (DSP).

In some embodiments, the processor 102 includes cache memory 104. Depending on the architecture, the processor 102 can have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores 107 using known cache coherency techniques. A register file 106 can be additionally included in processor 102 and may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). Some registers may be general-purpose registers, while other registers may be specific to the design of the processor 102.

In some embodiments, one or more processor(s) 102 are coupled with one or more interface bus(es) 110 to transmit communication signals such as address, data, or control signals between processor 102 and other components in the system 100. The interface bus 110, in one embodiment, can be a processor bus, such as a version of the Direct Media Interface (DMI) bus. However, processor busses are not limited to the DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI express), memory busses, or other types of interface busses. In one embodiment the processor(s) 102 include an integrated memory controller 116 and a platform controller hub 130. The memory controller 116 facilitates communication between a memory device and other components of the system 100, while the platform controller hub (PCH) 130 provides connections to I/O devices via a local I/O bus.

The memory device 120 can be a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment the memory device 120 can operate as system memory for the system 100, to store data 122 and instructions 121 for use when the one or more processors 102 executes an application or process. Memory controller 116 also couples with an optional external graphics processor 118, which may communicate with the one or more graphics processors 108 in processors 102 to perform graphics and media operations. In some embodiments, graphics, media, and or compute operations may be assisted by an accelerator 112 which is a coprocessor that can be configured to perform a specialized set of graphics, media, or compute operations. For example, in one embodiment the accelerator 112 is a matrix multiplication accelerator used to optimize machine learning or compute operations. In one embodiment the accelerator 112 is a ray-tracing accelerator that can be used to perform ray-tracing operations in concert with the graphics processor 108. In one embodiment, an external accelerator 119 may be used in place of or in concert with the accelerator 112.

In some embodiments a display device 111 can connect to the processor(s) 102. The display device 111 can be one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, embedded DisplayPort, MIPI, HDMI, etc.). In one embodiment the display device 111 can be a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

In some embodiments the platform controller hub 130 enables peripherals to connect to memory device 120 and processor 102 via a high-speed I/O bus. The I/O peripherals include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, touch sensors 125, a data storage device 124 (e.g., non-volatile memory, volatile memory, hard disk drive, flash memory, NAND, 3D NAND, 3D XPoint, etc.). The data storage device 124 can connect via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCI express). The touch sensors 125 can include touch screen sensors, pressure sensors, or fingerprint sensors. The wireless transceiver 126 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, 5G, or Long-Term Evolution (LTE) transceiver. The firmware interface 128 enables communication with system firmware, and can be, for example, a unified extensible firmware interface (UEFI). The network controller 134 can enable a network connection to a wired network. In some embodiments, a high-performance network controller (not shown) couples with the interface bus 110. The audio controller 146, in one embodiment, is a multi-channel high definition audio controller. In one embodiment the system 100 includes an optional legacy I/O controller 140 for coupling legacy (e.g., Personal System 2 (PS/2)) devices to the system. The platform controller hub 130 can also connect to one or more Universal Serial Bus (USB) controllers 142 connect input devices, such as keyboard and mouse 143 combinations, a camera 144, or other USB input devices.

It will be appreciated that the system 100 shown is exemplary and not limiting, as other types of data processing systems that are differently configured may also be used. For example, an instance of the memory controller 116 and platform controller hub 130 may be integrated into a discreet external graphics processor, such as the external graphics processor 118. In one embodiment the platform controller hub 130 and/or memory controller 116 may be external to the one or more processor(s) 102. For example, the system 100 can include an external memory controller 116 and platform controller hub 130, which may be configured as a memory controller hub and peripheral controller hub within a system chipset that is in communication with the processor(s) 102.

For example, circuit boards (“sleds”) can be used on which components such as CPUs, memory, and other components are placed are designed for increased thermal performance. In some examples, processing components such as the processors are located on a top side of a sled while near memory, such as DIMMs, are located on a bottom side of the sled. As a result of the enhanced airflow provided by this design, the components may operate at higher frequencies and power levels than in typical systems, thereby increasing performance. Furthermore, the sleds are configured to blindly mate with power and data communication cables in a rack, thereby enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. Similarly, individual components located on the sleds, such as processors, accelerators, memory, and data storage drives, are configured to be easily upgraded due to their increased spacing from each other. In the illustrative embodiment, the components additionally include hardware attestation features to prove their authenticity.

A data center can utilize a single network architecture (“fabric”) that supports multiple other network architectures including Ethernet and Omni-Path. The sleds can be coupled to switches via optical fibers, which provide higher bandwidth and lower latency than typical twisted pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high bandwidth, low latency interconnections and network architecture, the data center may, in use, pool resources, such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural network and/or artificial intelligence accelerators, etc.), and data storage drives that are physically disaggregated, and provide them to compute resources (e.g., processors) on an as needed basis, enabling the compute resources to access the pooled resources as if they were local.

A power supply or source can provide voltage and/or current to system 100 or any component or system described herein. In one example, the power supply includes an AC to DC (alternating current to direct current) adapter to plug into a wall outlet. Such AC power can be renewable energy (e.g., solar power) power source. In one example, power source includes a DC power source, such as an external AC to DC converter. In one example, power source or power supply includes wireless charging hardware to charge via proximity to a charging field. In one example, power source can include an internal battery, alternating current supply, motion-based power supply, solar power supply, or fuel cell source.

FIGS. 2A-2D illustrate computing systems and graphics processors provided by embodiments described herein. The elements of FIGS. 2A-2D having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

FIG. 2A is a block diagram of an embodiment of a processor 160 having one or more processor cores 162A-202N, an integrated memory controller 214, and an integrated graphics processor 168. Processor 160 can include additional cores up to and including additional core 162N represented by the dashed lined boxes. Each of processor cores 162A-202N includes one or more internal cache units 164A-204N. In some embodiments each processor core also has access to one or more shared cached units 166. The internal cache units 164A-204N and shared cache units 166 represent a cache memory hierarchy within the processor 160. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 166 and 164A-204N.

In some embodiments, processor 160 may also include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more PCI or PCI express busses. System agent core 210 provides management functionality for the various processor components. In some embodiments, system agent core 210 includes one or more integrated memory controllers 214 to manage access to various external memory devices (not shown).

In some embodiments, one or more of the processor cores 162A-202N include support for simultaneous multi-threading. In such embodiment, the system agent core 210 includes components for coordinating and operating cores 162A-202N during multi-threaded processing. System agent core 210 may additionally include a power control unit (PCU), which includes logic and components to regulate the power state of processor cores 162A-202N and graphics processor 168.

In some embodiments, processor 160 additionally includes graphics processor 168 to execute graphics processing operations. In some embodiments, the graphics processor 168 couples with the set of shared cache units 166, and the system agent core 210, including the one or more integrated memory controllers 214. In some embodiments, the system agent core 210 also includes a display controller 211 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 211 may also be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor 168.

In some embodiments, a ring-based interconnect unit 212 is used to couple the internal components of the processor 160. However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art. In some embodiments, graphics processor 168 couples with the ring interconnect 212 via an I/O link 213.

The exemplary I/O link 213 represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of the processor cores 162A-202N and graphics processor 168 can use embedded memory modules 218 as a shared Last Level Cache.

In some embodiments, processor cores 162A-202N are homogenous cores executing the same instruction set architecture. In another embodiment, processor cores 162A-202N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores 162A-202N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 162A-202N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. In one embodiment, processor cores 162A-202N are heterogeneous in terms of computational capability. Additionally, processor 160 can be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, in addition to other components.

FIG. 2B is a block diagram of hardware logic of a graphics processor core 219, according to some embodiments described herein. Elements of FIG. 2B having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. The graphics processor core 219, sometimes referred to as a core slice, can be one or multiple graphics cores within a modular graphics processor. The graphics processor core 219 is exemplary of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. Each graphics processor core 219 can include a fixed function block 230 coupled with multiple sub-cores 221A-221F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed function logic.

In some embodiments, the fixed function block 230 includes a geometry/fixed function pipeline 231 that can be shared by all sub-cores in the graphics processor core 219, for example, in lower performance and/or lower power graphics processor implementations. In various embodiments, the geometry/fixed function pipeline 231 includes a 3D fixed function pipeline (e.g., 3D pipeline 312 as in FIG. 3 and FIG. 4, described below) a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager, which manages unified return buffers (e.g., unified return buffer 418 in FIG. 4, as described below).

In one embodiment the fixed function block 230 also includes a graphics SoC interface 232, a graphics microcontroller 233, and a media pipeline 234. The graphics SoC interface 232 provides an interface between the graphics processor core 219 and other processor cores within a system on a chip integrated circuit. The graphics microcontroller 233 is a programmable sub-processor that is configurable to manage various functions of the graphics processor core 219, including thread dispatch, scheduling, and pre-emption. The media pipeline 234 (e.g., media pipeline 316 of FIG. 3 and FIG. 4) includes logic to facilitate the decoding, encoding, pre-processing, and/or post-processing of multimedia data, including image and video data. The media pipeline 234 implement media operations via requests to compute or sampling logic within the sub-cores 221-221F.

In one embodiment the SoC interface 232 enables the graphics processor core 219 to communicate with general-purpose application processor cores (e.g., CPUs) and/or other components within an SoC, including memory hierarchy elements such as a shared last level cache memory, the system RAM, and/or embedded on-chip or on-package DRAM. The SoC interface 232 can also enable communication with fixed function devices within the SoC, such as camera imaging pipelines, and enables the use of and/or implements global memory atomics that may be shared between the graphics processor core 219 and CPUs within the SoC. The SoC interface 232 can also implement power management controls for the graphics processor core 219 and enable an interface between a clock domain of the graphic core 219 and other clock domains within the SoC. In one embodiment the SoC interface 232 enables receipt of command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. The commands and instructions can be dispatched to the media pipeline 234, when media operations are to be performed, or a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline 231, geometry and fixed function pipeline 237) when graphics processing operations are to be performed.

The graphics microcontroller 233 can be configured to perform various scheduling and management tasks for the graphics processor core 219. In one embodiment the graphics microcontroller 233 can perform graphics and/or compute workload scheduling on the various graphics parallel engines within execution unit (EU) arrays 222A-222F, 224A-224F within the sub-cores 221A-221F. In this scheduling model, host software executing on a CPU core of an SoC including the graphics processor core 219 can submit workloads one of multiple graphic processor doorbells, which invokes a scheduling operation on the appropriate graphics engine. Scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre-empting existing workloads running on an engine, monitoring progress of a workload, and notifying host software when a workload is complete. In one embodiment the graphics microcontroller 233 can also facilitate low-power or idle states for the graphics processor core 219, providing the graphics processor core 219 with the ability to save and restore registers within the graphics processor core 219 across low-power state transitions independently from the operating system and/or graphics driver software on the system.

The graphics processor core 219 may have greater than or fewer than the illustrated sub-cores 221A-221F, up to N modular sub-cores. For each set of N sub-cores, the graphics processor core 219 can also include shared function logic 235, shared and/or cache memory 236, a geometry/fixed function pipeline 237, as well as additional fixed function logic 238 to accelerate various graphics and compute processing operations. The shared function logic 235 can include logic units associated with the shared function logic 420 of FIG. 4 (e.g., sampler, math, and/or inter-thread communication logic) that can be shared by each N sub-cores within the graphics processor core 219. The shared and/or cache memory 236 can be a last-level cache for the set of N sub-cores 221A-221F within the graphics processor core 219, and can also serve as shared memory that is accessible by multiple sub-cores. The geometry/fixed function pipeline 237 can be included instead of the geometry/fixed function pipeline 231 within the fixed function block 230 and can include the same or similar logic units.

In one embodiment the graphics processor core 219 includes additional fixed function logic 238 that can include various fixed function acceleration logic for use by the graphics processor core 219. In one embodiment the additional fixed function logic 238 includes an additional geometry pipeline for use in position only shading. In position-only shading, two geometry pipelines exist, the full geometry pipeline within the geometry/fixed function pipeline 238, 231, and a cull pipeline, which is an additional geometry pipeline which may be included within the additional fixed function logic 238. In one embodiment the cull pipeline is a trimmed down version of the full geometry pipeline. The full pipeline and the cull pipeline can execute different instances of the same application, each instance having a separate context. Position only shading can hide long cull runs of discarded triangles, enabling shading to be completed earlier in some instances. For example and in one embodiment the cull pipeline logic within the additional fixed function logic 238 can execute position shaders in parallel with the main application and generally generates critical results faster than the full pipeline, as the cull pipeline fetches and shades only the position attribute of the vertices, without performing rasterization and rendering of the pixels to the frame buffer. The cull pipeline can use the generated critical results to compute visibility information for all the triangles without regard to whether those triangles are culled. The full pipeline (which in this instance may be referred to as a replay pipeline) can consume the visibility information to skip the culled triangles to shade only the visible triangles that are finally passed to the rasterization phase.

In one embodiment the additional fixed function logic 238 can also include machine-learning acceleration logic, such as fixed function matrix multiplication logic, for implementations including optimizations for machine learning training or inferencing.

Within each graphics sub-core 221A-221F includes a set of execution resources that may be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader programs. The graphics sub-cores 221A-221F include multiple EU arrays 222A-222F, 224A-224F, thread dispatch and inter-thread communication (TD/IC) logic 223A-223F, a 3D (e.g., texture) sampler 225A-225F, a media sampler 166A-206F, a shader processor 227A-227F, and shared local memory (SLM) 228A-228F. The EU arrays 222A-222F, 224A-224F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer/fixed-point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute shader programs. The TD/IC logic 223A-223F performs local thread dispatch and thread control operations for the execution units within a sub-core and facilitate communication between threads executing on the execution units of the sub-core. The 3D sampler 225A-225F can read texture or other 3D graphics related data into memory. The 3D sampler can read texture data differently based on a configured sample state and the texture format associated with a given texture. The media sampler 166A-206F can perform similar read operations based on the type and format associated with media data. In one embodiment, each graphics sub-core 221A-221F can alternately include a unified 3D and media sampler. Threads executing on the execution units within each of the sub-cores 221A-221F can make use of shared local memory 228A-228F within each sub-core, to enable threads executing within a thread group to execute using a common pool of on-chip memory.

FIG. 2C illustrates a graphics processing unit (GPU) 239 that includes dedicated sets of graphics processing resources arranged into multi-core groups 240A-240N. While the details of only a single multi-core group 240A are provided, it will be appreciated that the other multi-core groups 240B-240N may be equipped with the same or similar sets of graphics processing resources.

As illustrated, a multi-core group 240A may include a set of graphics cores 243, a set of tensor cores 244, and a set of ray tracing cores 245. A scheduler/dispatcher 241 schedules and dispatches the graphics threads for execution on the various cores 243, 244, 245. A set of register files 242 store operand values used by the cores 243, 244, 245 when executing the graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and/or floating point data elements) and tile registers for storing tensor/matrix values. In one embodiment, the tile registers are implemented as combined sets of vector registers.

One or more combined level 1 (L1) caches and shared memory units 247 store graphics data such as texture data, vertex data, pixel data, ray data, bounding volume data, etc., locally within each multi-core group 240A. One or more texture units 247 can also be used to perform texturing operations, such as texture mapping and sampling. A Level 2 (L2) cache 253 shared by all or a subset of the multi-core groups 240A-240N stores graphics data and/or instructions for multiple concurrent graphics threads. As illustrated, the L2 cache 253 may be shared across a plurality of multi-core groups 240A-240N. One or more memory controllers 248 couple the GPU 239 to a memory 249 which may be a system memory (e.g., DRAM) and/or a dedicated graphics memory (e.g., GDDR6 memory).

Input/output (I/O) circuitry 250 couples the GPU 239 to one or more I/O devices 252 such as digital signal processors (DSPs), network controllers, or user input devices. An on-chip interconnect may be used to couple the I/O devices 252 to the GPU 239 and memory 249. One or more I/O memory management units (IOMMUs) 251 of the I/O circuitry 250 couple the I/O devices 252 directly to the system memory 249. In one embodiment, the IOMMU 251 manages multiple sets of page tables to map virtual addresses to physical addresses in system memory 249. In this embodiment, the I/O devices 252, CPU(s) 246, and GPU(s) 239 may share the same virtual address space.

In one implementation, the IOMMU 251 supports virtualization. In this case, it may manage a first set of page tables to map guest/graphics virtual addresses to guest/graphics physical addresses and a second set of page tables to map the guest/graphics physical addresses to system/host physical addresses (e.g., within system memory 249). The base addresses of each of the first and second sets of page tables may be stored in control registers and swapped out on a context switch (e.g., so that the new context is provided with access to the relevant set of page tables). While not illustrated in FIG. 2C, each of the cores 243, 244, 245 and/or multi-core groups 240A-240N may include translation lookaside buffers (TLBs) to cache guest virtual to guest physical translations, guest physical to host physical translations, and guest virtual to host physical translations.

In one embodiment, the CPUs 246, GPUs 239, and I/O devices 252 are integrated on a single semiconductor chip and/or chip package. The illustrated memory 249 may be integrated on the same chip or may be coupled to the memory controllers 248 via an off-chip interface. In one implementation, the memory 249 comprises GDDR6 memory which shares the same virtual address space as other physical system-level memories, although the underlying principles of the invention are not limited to this specific implementation.

In one embodiment, the tensor cores 244 include a plurality of execution units specifically designed to perform matrix operations, which are the fundamental compute operation used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for neural network training and inferencing. The tensor cores 244 may perform matrix processing using a variety of operand precisions including single precision floating-point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half-bytes (4 bits). In one embodiment, a neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames, to construct a high-quality final image.

In deep learning implementations, parallel matrix multiplication work may be scheduled for execution on the tensor cores 244. The training of neural networks, in particular, requires a significant number of matrix dot product operations. In order to process an inner-product formulation of an N×N×N matrix multiply, the tensor cores 244 may include at least N dot-product processing elements. Before the matrix multiply begins, one entire matrix is loaded into tile registers and at least one column of a second matrix is loaded each cycle for N cycles. Each cycle, there are N dot products that are processed.

Matrix elements may be stored at different precisions depending on the particular implementation, including 16-bit words, 8-bit bytes (e.g., INT8) and 4-bit half-bytes (e.g., INT4). Different precision modes may be specified for the tensor cores 244 to ensure that the most efficient precision is used for different workloads (e.g., such as inferencing workloads which can tolerate quantization to bytes and half-bytes).

In one embodiment, the ray tracing cores 245 accelerate ray tracing operations for both real-time ray tracing and non-real-time ray tracing implementations. In particular, the ray tracing cores 245 include ray traversal/intersection circuitry for performing ray traversal using bounding volume hierarchies (BVHs) and identifying intersections between rays and primitives enclosed within the BVH volumes. The ray tracing cores 245 may also include circuitry for performing depth testing and culling (e.g., using a Z buffer or similar arrangement). In one implementation, the ray tracing cores 245 perform traversal and intersection operations in concert with the image denoising techniques described herein, at least a portion of which may be executed on the tensor cores 244. For example, in one embodiment, the tensor cores 244 implement a deep learning neural network to perform denoising of frames generated by the ray tracing cores 245. However, the CPU(s) 246, graphics cores 243, and/or ray tracing cores 245 may also implement all or a portion of the denoising and/or deep learning algorithms.

In addition, as described above, a distributed approach to denoising may be employed in which the GPU 239 is in a computing device coupled to other computing devices over a network or high speed interconnect. In this embodiment, the interconnected computing devices share neural network learning/training data to improve the speed with which the overall system learns to perform denoising for different types of image frames and/or different graphics applications.

In one embodiment, the ray tracing cores 245 process all BVH traversal and ray-primitive intersections, saving the graphics cores 243 from being overloaded with thousands of instructions per ray. In one embodiment, each ray tracing core 245 includes a first set of specialized circuitries for performing bounding box tests (e.g., for traversal operations) and a second set of specialized circuitry for performing the ray-triangle intersection tests (e.g., intersecting rays which have been traversed). Thus, in one embodiment, the multi-core group 240A can simply launch a ray probe, and the ray tracing cores 245 independently perform ray traversal and intersection and return hit data (e.g., a hit, no hit, multiple hits, etc.) to the thread context. The other cores 243, 244 are freed to perform other graphics or compute work while the ray tracing cores 245 perform the traversal and intersection operations.

In one embodiment, each ray tracing core 245 includes a traversal unit to perform BVH testing operations and an intersection unit which performs ray-primitive intersection tests. The intersection unit generates a “hit”, “no hit”, or “multiple hit” response, which it provides to the appropriate thread. During the traversal and intersection operations, the execution resources of the other cores (e.g., graphics cores 243 and tensor cores 244) are freed to perform other forms of graphics work.

In one particular embodiment described below, a hybrid rasterization/ray tracing approach is used in which work is distributed between the graphics cores 243 and ray tracing cores 245.

In one embodiment, the ray tracing cores 245 (and/or other cores 243, 244) include hardware support for a ray tracing instruction set such as Microsoft's DirectX Ray Tracing (DXR) which includes a DispatchRays command, as well as ray-generation, closest-hit, any-hit, and miss shaders, which enable the assignment of unique sets of shaders and textures for each object. Another ray tracing platform which may be supported by the ray tracing cores 245, graphics cores 243 and tensor cores 244 is Vulkan 1.1.85. Note, however, that the underlying principles of the invention are not limited to any particular ray tracing ISA.

In general, the various cores 245, 244, 243 may support a ray tracing instruction set that includes instructions/functions for ray generation, closest hit, any hit, ray-primitive intersection, per-primitive and hierarchical bounding box construction, miss, visit, and exceptions. More specifically, one embodiment includes ray tracing instructions to perform the following functions:

-   -   Ray Generation—Ray generation instructions may be executed for         each pixel, sample, or other user-defined work assignment.     -   Closest Hit—A closest hit instruction may be executed to locate         the closest intersection point of a ray with primitives within a         scene.     -   Any Hit—An any hit instruction identifies multiple intersections         between a ray and primitives within a scene, potentially to         identify a new closest intersection point.     -   Intersection—An intersection instruction performs a         ray-primitive intersection test and outputs a result.     -   Per-primitive Bounding box Construction—This instruction builds         a bounding box around a given primitive or group of primitives         (e.g., when building a new BVH or other acceleration data         structure).     -   Miss—Indicates that a ray misses all geometry within a scene, or         specified region of a scene.     -   Visit—Indicates the children volumes a ray will traverse.     -   Exceptions—Includes various types of exception handlers (e.g.,         invoked for various error conditions).

FIG. 2D is a block diagram of general purpose graphics processing unit (GPGPU) 270 that can be configured as a graphics processor and/or compute accelerator, according to embodiments described herein. The GPGPU 270 can interconnect with host processors (e.g., one or more CPU(s) 246) and memory 271, 272 via one or more system and/or memory busses. In one embodiment the memory 271 is system memory that may be shared with the one or more CPU(s) 246, while memory 272 is device memory that is dedicated to the GPGPU 270. In one embodiment, components within the GPGPU 270 and device memory 272 may be mapped into memory addresses that are accessible to the one or more CPU(s) 246. Access to memory 271 and 272 may be facilitated via a memory controller 268. In one embodiment the memory controller 268 includes an internal direct memory access (DMA) controller 269 or can include logic to perform operations that would otherwise be performed by a DMA controller.

The GPGPU 270 includes multiple cache memories, including an L2 cache 253, L1 cache 254, an instruction cache 255, and shared memory 256, at least a portion of which may also be partitioned as a cache memory. The GPGPU 270 also includes multiple compute units 260A-260N. Each compute unit 260A-260N includes a set of vector registers 261, scalar registers 262, vector logic units 263, and scalar logic units 264. The compute units 260A-260N can also include local shared memory 265 and a program counter 266. The compute units 260A-260N can couple with a constant cache 267, which can be used to store constant data, which is data that will not change during the run of kernel or shader program that executes on the GPGPU 270. In one embodiment the constant cache 267 is a scalar data cache and cached data can be fetched directly into the scalar registers 262.

During operation, the one or more CPU(s) 246 can write commands into registers or memory in the GPGPU 270 that has been mapped into an accessible address space. The command processors 257 can read the commands from registers or memory and determine how those commands will be processed within the GPGPU 270. A thread dispatcher 258 can then be used to dispatch threads to the compute units 260A-260N to perform those commands Each compute unit 260A-260N can execute threads independently of the other compute units. Additionally, each compute unit 260A-260N can be independently configured for conditional computation and can conditionally output the results of computation to memory. The command processors 257 can interrupt the one or more CPU(s) 246 when the submitted commands are complete.

FIGS. 3A-3C illustrate block diagrams of additional graphics processor and compute accelerator architectures provided by embodiments described herein. The elements of FIGS. 3A-3C having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

FIG. 3A is a block diagram of a graphics processor 300, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores, or other semiconductor devices such as, but not limited to, memory devices or network interfaces. In some embodiments, the graphics processor communicates via a memory mapped I/O interface to registers on the graphics processor and with commands placed into the processor memory. In some embodiments, graphics processor 300 includes a memory interface 314 to access memory. Memory interface 314 can be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory.

In some embodiments, graphics processor 300 also includes a display controller 302 to drive display output data to a display device 318. Display controller 302 includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. The display device 318 can be an internal or external display device. In one embodiment the display device 318 is a head mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, graphics processor 300 includes a video codec engine 306 to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, H.265/HEVC, Alliance for Open Media (AOMedia) VP8, VP9, as well as the Society of Motion Picture & Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE) 310. In some embodiments, GPE 310 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

In some embodiments, GPE 310 includes a 3D pipeline 312 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). The 3D pipeline 312 includes programmable and fixed function elements that perform various tasks within the element and/or spawn execution threads to a 3D/Media sub-system 315. While 3D pipeline 312 can be used to perform media operations, an embodiment of GPE 310 also includes a media pipeline 316 that is specifically used to perform media operations, such as video post-processing and image enhancement.

In some embodiments, media pipeline 316 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine 306. In some embodiments, media pipeline 316 additionally includes a thread spawning unit to spawn threads for execution on 3D/Media sub-system 315. The spawned threads perform computations for the media operations on one or more graphics execution units included in 3D/Media sub-system 315.

In some embodiments, 3D/Media subsystem 315 includes logic for executing threads spawned by 3D pipeline 312 and media pipeline 316. In one embodiment, the pipelines send thread execution requests to 3D/Media subsystem 315, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units to process the 3D and media threads. In some embodiments, 3D/Media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and to store output data.

FIG. 3B illustrates a graphics processor 320 having a tiled architecture, according to embodiments described herein. In one embodiment the graphics processor 320 includes a graphics processing engine cluster 322 having multiple instances of the graphics processing engine 310 of FIG. 3A within a graphics engine tile 310A-310D. Each graphics engine tile 310A-310D can be interconnected via a set of tile interconnects 323A-323F. Each graphics engine tile 310A-310D can also be connected to a memory module or memory device 326A-326D via memory interconnects 325A-325D. The memory devices 326A-326D can use any graphics memory technology. For example, the memory devices 326A-326D may be graphics double data rate (GDDR) memory. The memory devices 326A-326D, in one embodiment, are high-bandwidth memory (HBM) modules that can be on-die with their respective graphics engine tile 310A-310D. In one embodiment the memory devices 326A-326D are stacked memory devices that can be stacked on top of their respective graphics engine tile 310A-310D. In one embodiment, each graphics engine tile 310A-310D and associated memory 326A-326D reside on separate chiplets, which are bonded to a base die or base substrate, as described on further detail in FIGS. 11B-11D.

The graphics processing engine cluster 322 can connect with an on-chip or on-package fabric interconnect 324. The fabric interconnect 324 can enable communication between graphics engine tiles 310A-310D and components such as the video codec 306 and one or more copy engines 304. The copy engines 304 can be used to move data out of, into, and between the memory devices 326A-326D and memory that is external to the graphics processor 320 (e.g., system memory). The fabric interconnect 324 can also be used to interconnect the graphics engine tiles 310A-310D. The graphics processor 320 may optionally include a display controller 302 to enable a connection with an external display device 318. The graphics processor may also be configured as a graphics or compute accelerator. In the accelerator configuration, the display controller 302 and display device 318 may be omitted.

The graphics processor 320 can connect to a host system via a host interface 328. The host interface 328 can enable communication between the graphics processor 320, system memory, and/or other system components. The host interface 328 can be, for example a PCI express bus or another type of host system interface.

FIG. 3C illustrates a compute accelerator 330, according to embodiments described herein. The compute accelerator 330 can include architectural similarities with the graphics processor 320 of FIG. 3B and is optimized for compute acceleration. A compute engine cluster 332 can include a set of compute engine tiles 340A-340D that include execution logic that is optimized for parallel or vector-based general-purpose compute operations. In some embodiments, the compute engine tiles 340A-340D do not include fixed function graphics processing logic, although in one embodiment one or more of the compute engine tiles 340A-340D can include logic to perform media acceleration. The compute engine tiles 340A-340D can connect to memory 326A-326D via memory interconnects 325A-325D. The memory 326A-326D and memory interconnects 325A-325D may be similar technology as in graphics processor 320, or can be different. The graphics compute engine tiles 340A-340D can also be interconnected via a set of tile interconnects 323A-323F and may be connected with and/or interconnected by a fabric interconnect 324. In one embodiment the compute accelerator 330 includes a large L3 cache 336 that can be configured as a device-wide cache. The compute accelerator 330 can also connect to a host processor and memory via a host interface 328 in a similar manner as the graphics processor 320 of FIG. 3B.

Graphics Processing Engine

FIG. 4 is a block diagram of a graphics processing engine 410 of a graphics processor in accordance with some embodiments. In one embodiment, the graphics processing engine (GPE) 410 is a version of the GPE 310 shown in FIG. 3A, and may also represent a graphics engine tile 310A-310D of FIG. 3B. Elements of FIG. 4 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. For example, the 3D pipeline 312 and media pipeline 316 of FIG. 3A are illustrated. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included within the GPE 410. For example, and in at least one embodiment, a separate media and/or image processor is coupled to the GPE 410.

In some embodiments, GPE 410 couples with or includes a command streamer 403, which provides a command stream to the 3D pipeline 312 and/or media pipelines 316. In some embodiments, command streamer 403 is coupled with memory, which can be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer 403 receives commands from the memory and sends the commands to 3D pipeline 312 and/or media pipeline 316. The commands are directives fetched from a ring buffer, which stores commands for the 3D pipeline 312 and media pipeline 316. In one embodiment, the ring buffer can additionally include batch command buffers storing batches of multiple commands. The commands for the 3D pipeline 312 can also include references to data stored in memory, such as but not limited to vertex and geometry data for the 3D pipeline 312 and/or image data and memory objects for the media pipeline 316. The 3D pipeline 312 and media pipeline 316 process the commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to a graphics core array 414. In one embodiment the graphics core array 414 include one or more blocks of graphics cores (e.g., graphics core(s) 415A, graphics core(s) 415B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources that includes general-purpose and graphics specific execution logic to perform graphics and compute operations, as well as fixed function texture processing and/or machine learning and artificial intelligence acceleration logic.

In various embodiments the 3D pipeline 312 can include fixed function and programmable logic to process one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing the instructions and dispatching execution threads to the graphics core array 414. The graphics core array 414 provides a unified block of execution resources for use in processing these shader programs. Multi-purpose execution logic (e.g., execution units) within the graphics core(s) 415A-414B of the graphic core array 414 includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders.

In some embodiments, the graphics core array 414 includes execution logic to perform media functions, such as video and/or image processing. In one embodiment, the execution units include general-purpose logic that is programmable to perform parallel general-purpose computational operations, in addition to graphics processing operations. The general-purpose logic can perform processing operations in parallel or in conjunction with general-purpose logic within the processor core(s) 107 of FIG. 1 or core 162A-202N as in FIG. 2A.

Output data generated by threads executing on the graphics core array 414 can output data to memory in a unified return buffer (URB) 418. The URB 418 can store data for multiple threads. In some embodiments the URB 418 may be used to send data between different threads executing on the graphics core array 414. In some embodiments the URB 418 may additionally be used for synchronization between threads on the graphics core array and fixed function logic within the shared function logic 420.

In some embodiments, graphics core array 414 is scalable, such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 410. In one embodiment the execution resources are dynamically scalable, such that execution resources may be enabled or disabled as needed.

The graphics core array 414 couples with shared function logic 420 that includes multiple resources that are shared between the graphics cores in the graphics core array. The shared functions within the shared function logic 420 are hardware logic units that provide specialized supplemental functionality to the graphics core array 414. In various embodiments, shared function logic 420 includes but is not limited to sampler 421, math 422, and inter-thread communication (ITC) 423 logic. Additionally, some embodiments implement one or more cache(s) 425 within the shared function logic 420.

A shared function is implemented at least in a case where the demand for a given specialized function is insufficient for inclusion within the graphics core array 414. Instead a single instantiation of that specialized function is implemented as a stand-alone entity in the shared function logic 420 and shared among the execution resources within the graphics core array 414. The precise set of functions that are shared between the graphics core array 414 and included within the graphics core array 414 varies across embodiments. In some embodiments, specific shared functions within the shared function logic 420 that are used extensively by the graphics core array 414 may be included within shared function logic 416 within the graphics core array 414. In various embodiments, the shared function logic 416 within the graphics core array 414 can include some or all logic within the shared function logic 420. In one embodiment, all logic elements within the shared function logic 420 may be duplicated within the shared function logic 416 of the graphics core array 414. In one embodiment the shared function logic 420 is excluded in favor of the shared function logic 416 within the graphics core array 414.

Execution Units

FIGS. 5A-5B illustrate thread execution logic 500 including an array of processing elements employed in a graphics processor core according to embodiments described herein. Elements of FIGS. 5A-5B having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. FIG. 5A-5B illustrates an overview of thread execution logic 500, which may be representative of hardware logic illustrated with each sub-core 221A-221F of FIG. 2B. FIG. 5A is representative of an execution unit within a general-purpose graphics processor, while FIG. 5B is representative of an execution unit that may be used within a compute accelerator.

As illustrated in FIG. 5A, in some embodiments thread execution logic 500 includes a shader processor 502, a thread dispatcher 504, instruction cache 506, a scalable execution unit array including a plurality of execution units 508A-508N, a sampler 510, shared local memory 511, a data cache 512, and a data port 514. In one embodiment the scalable execution unit array can dynamically scale by enabling or disabling one or more execution units (e.g., any of execution units 508A, 508B, 508C, 508D, through 508N-1 and 508N) based on the computational requirements of a workload. In one embodiment the included components are interconnected via an interconnect fabric that links to each of the components. In some embodiments, thread execution logic 500 includes one or more connections to memory, such as system memory or cache memory, through one or more of instruction cache 506, data port 514, sampler 510, and execution units 508A-508N. In some embodiments, each execution unit (e.g. 508A) is a stand-alone programmable general-purpose computational unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 508A-508N is scalable to include any number individual execution units.

In some embodiments, the execution units 508A-508N are primarily used to execute shader programs. A shader processor 502 can process the various shader programs and dispatch execution threads associated with the shader programs via a thread dispatcher 504. In one embodiment the thread dispatcher includes logic to arbitrate thread initiation requests from the graphics and media pipelines and instantiate the requested threads on one or more execution unit in the execution units 508A-508N. For example, a geometry pipeline can dispatch vertex, tessellation, or geometry shaders to the thread execution logic for processing. In some embodiments, thread dispatcher 504 can also process runtime thread spawning requests from the executing shader programs.

In some embodiments, the execution units 508A-508N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general-purpose processing (e.g., compute and media shaders). Each of the execution units 508A-508N is capable of multi-issue single instruction multiple data (SIMD) execution and multi-threaded operation enables an efficient execution environment in the face of higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread-state. Execution is multi-issue per clock to pipelines capable of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscellaneous operations. While waiting for data from memory or one of the shared functions, dependency logic within the execution units 508A-508N causes a waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources may be devoted to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, fragment shader, or another type of shader program, including a different vertex shader. Various embodiments can apply to use execution by use of Single Instruction Multiple Thread (SIMT) as an alternate to use of SIMD or in addition to use of SIMD. Reference to a SIMD core or operation can apply also to SIMT or apply to SIMD in combination with SIMT.

Each execution unit in execution units 508A-508N operates on arrays of data elements. The number of data elements is the “execution size,” or the number of channels for the instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In some embodiments, execution units 508A-508N support integer and floating-point data types.

The execution unit instruction set includes SIMD instructions. The various data elements can be stored as a packed data type in a register and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register and the execution unit operates on the vector as four separate 54-bit packed data elements (Quad-Word (QW) size data elements), eight separate 32-bit packed data elements (Double Word (DW) size data elements), sixteen separate 16-bit packed data elements (Word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

In one embodiment one or more execution units can be combined into a fused execution unit 509A-509N having thread control logic (507A-507N) that is common to the fused EUs. Multiple EUs can be fused into an EU group. Each EU in the fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group can vary according to embodiments. Additionally, various SIMD widths can be performed per-EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit 509A-509N includes at least two execution units. For example, fused execution unit 509A includes a first EU 508A, second EU 508B, and thread control logic 507A that is common to the first EU 508A and the second EU 508B. The thread control logic 507A controls threads executed on the fused graphics execution unit 509A, allowing each EU within the fused execution units 509A-509N to execute using a common instruction pointer register.

One or more internal instruction caches (e.g., 506) are included in the thread execution logic 500 to cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 512) are included to cache thread data during thread execution. Threads executing on the execution logic 500 can also store explicitly managed data in the shared local memory 511. In some embodiments, a sampler 510 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler 510 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to an execution unit.

During execution, the graphics and media pipelines send thread initiation requests to thread execution logic 500 via thread spawning and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 502 is invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). In some embodiments, a pixel shader or fragment shader calculates the values of the various vertex attributes that are to be interpolated across the rasterized object. In some embodiments, pixel processor logic within the shader processor 502 then executes an application programming interface (API)-supplied pixel or fragment shader program. To execute the shader program, the shader processor 502 dispatches threads to an execution unit (e.g., 508A) via thread dispatcher 504. In some embodiments, shader processor 502 uses texture sampling logic in the sampler 510 to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing.

In some embodiments, the data port 514 provides a memory access mechanism for the thread execution logic 500 to output processed data to memory for further processing on a graphics processor output pipeline. In some embodiments, the data port 514 includes or couples to one or more cache memories (e.g., data cache 512) to cache data for memory access via the data port.

In one embodiment, the execution logic 500 can also include a ray tracer 505 that can provide ray tracing acceleration functionality. The ray tracer 505 can support a ray tracing instruction set that includes instructions/functions for ray generation. The ray tracing instruction set can be similar to or different from the ray-tracing instruction set supported by the ray tracing cores 245 in FIG. 2C.

FIG. 5B illustrates exemplary internal details of an execution unit 508, according to embodiments. A graphics execution unit 508 can include an instruction fetch unit 537, a general register file array (GRF) 524, an architectural register file array (ARF) 526, a thread arbiter 522, a send unit 530, a branch unit 532, a set of SIMD floating point units (FPUs) 534, and in one embodiment a set of dedicated integer SIMD ALUs 535. The GRF 524 and ARF 526 includes the set of general register files and architecture register files associated with each simultaneous hardware thread that may be active in the graphics execution unit 508. In one embodiment, per thread architectural state is maintained in the ARF 526, while data used during thread execution is stored in the GRF 524. The execution state of each thread, including the instruction pointers for each thread, can be held in thread-specific registers in the ARF 526.

In one embodiment the graphics execution unit 508 has an architecture that is a combination of Simultaneous Multi-Threading (SMT) and fine-grained Interleaved Multi-Threading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and number of registers per execution unit, where execution unit resources are divided across logic used to execute multiple simultaneous threads. The number of logical threads that may be executed by the graphics execution unit 508 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

In one embodiment, the graphics execution unit 508 can co-issue multiple instructions, which may each be different instructions. The thread arbiter 522 of the graphics execution unit thread 508 can dispatch the instructions to one of the send unit 530, branch unit 532, or SIMD FPU(s) 534 for execution. Each execution thread can access 128 general-purpose registers within the GRF 524, where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. In one embodiment, each execution unit thread has access to 4 Kbytes within the GRF 524, although embodiments are not so limited, and greater or fewer register resources may be provided in other embodiments. In one embodiment the graphics execution unit 508 is partitioned into seven hardware threads that can independently perform computational operations, although the number of threads per execution unit can also vary according to embodiments. For example, in one embodiment up to 16 hardware threads are supported. In an embodiment in which seven threads may access 4 Kbytes, the GRF 524 can store a total of 28 Kbytes. Where 16 threads may access 4Kbytes, the GRF 524 can store a total of 64Kbytes. Flexible addressing modes can permit registers to be addressed together to build effectively wider registers or to represent strided rectangular block data structures.

In one embodiment, memory operations, sampler operations, and other longer-latency system communications are dispatched via “send” instructions that are executed by the message passing send unit 530. In one embodiment, branch instructions are dispatched to a dedicated branch unit 532 to facilitate SIMD divergence and eventual convergence.

In one embodiment the graphics execution unit 508 includes one or more SIMD floating point units (FPU(s)) 534 to perform floating-point operations. In one embodiment, the FPU(s) 534 also support integer computation. In one embodiment the FPU(s) 534 can SIMD execute up to M number of 32-bit floating-point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating-point operations. In one embodiment, at least one of the FPU(s) provides extended math capability to support high-throughput transcendental math functions and double precision 54-bit floating-point. In some embodiments, a set of 8-bit integer SIMD ALUs 535 are also present, and may be specifically optimized to perform operations associated with machine learning computations.

In one embodiment, arrays of multiple instances of the graphics execution unit 508 can be instantiated in a graphics sub-core grouping (e.g., a sub-slice). For scalability, product architects can choose the exact number of execution units per sub-core grouping. In one embodiment the execution unit 508 can execute instructions across a plurality of execution channels. In a further embodiment, each thread executed on the graphics execution unit 508 is executed on a different channel.

FIG. 6 illustrates an additional execution unit 600, according to an embodiment. The execution unit 600 may be a compute-optimized execution unit for use in, for example, a compute engine tile 340A-340D as in FIG. 3C, but is not limited as such. Variants of the execution unit 600 may also be used in a graphics engine tile 310A-310D as in FIG. 3B. In one embodiment, the execution unit 600 includes a thread control unit 601, a thread state unit 602, an instruction fetch/prefetch unit 603, and an instruction decode unit 604. The execution unit 600 additionally includes a register file 606 that stores registers that can be assigned to hardware threads within the execution unit. The execution unit 600 additionally includes a send unit 607 and a branch unit 608. In one embodiment, the send unit 607 and branch unit 608 can operate similarly as the send unit 530 and a branch unit 532 of the graphics execution unit 508 of FIG. 5B.

The execution unit 600 also includes a compute unit 610 that includes multiple different types of functional units. In one embodiment the compute unit 610 includes an ALU unit 611 that includes an array of arithmetic logic units. The ALU unit 611 can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating point operations. Integer and floating point operations may be performed simultaneously. The compute unit 610 can also include a systolic array 612, and a math unit 613. The systolic array 612 includes a W wide and D deep network of data processing units that can be used to perform vector or other data-parallel operations in a systolic manner In one embodiment the systolic array 612 can be configured to perform matrix operations, such as matrix dot product operations. In one embodiment the systolic array 612 support 16-bit floating point operations, as well as 8-bit and 4-bit integer operations. In one embodiment the systolic array 612 can be configured to accelerate machine learning operations. In such embodiments, the systolic array 612 can be configured with support for the bfloat 16-bit floating point format. In one embodiment, a math unit 613 can be included to perform a specific subset of mathematical operations in an efficient and lower-power manner than then ALU unit 611. The math unit 613 can include a variant of math logic that may be found in shared function logic of a graphics processing engine provided by other embodiments (e.g., math logic 422 of the shared function logic 420 of FIG. 4). In one embodiment the math unit 613 can be configured to perform 32-bit and 64-bit floating point operations.

The thread control unit 601 includes logic to control the execution of threads within the execution unit. The thread control unit 601 can include thread arbitration logic to start, stop, and preempt execution of threads within the execution unit 600. The thread state unit 602 can be used to store thread state for threads assigned to execute on the execution unit 600. Storing the thread state within the execution unit 600 enables the rapid pre-emption of threads when those threads become blocked or idle. The instruction fetch/prefetch unit 603 can fetch instructions from an instruction cache of higher level execution logic (e.g., instruction cache 506 as in FIG. 5A). The instruction fetch/prefetch unit 603 can also issue prefetch requests for instructions to be loaded into the instruction cache based on an analysis of currently executing threads. The instruction decode unit 604 can be used to decode instructions to be executed by the compute units. In one embodiment, the instruction decode unit 604 can be used as a secondary decoder to decode complex instructions into constituent micro-operations.

The execution unit 600 additionally includes a register file 606 that can be used by hardware threads executing on the execution unit 600. Registers in the register file 606 can be divided across the logic used to execute multiple simultaneous threads within the compute unit 610 of the execution unit 600. The number of logical threads that may be executed by the graphics execution unit 600 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread. The size of the register file 606 can vary across embodiments based on the number of supported hardware threads. In one embodiment, register renaming may be used to dynamically allocate registers to hardware threads.

FIG. 7 is a block diagram illustrating a graphics processor instruction formats 700 according to some embodiments. In one or more embodiment, the graphics processor execution units support an instruction set having instructions in multiple formats. The solid lined boxes illustrate the components that are generally included in an execution unit instruction, while the dashed lines include components that are optional or that are only included in a sub-set of the instructions. In some embodiments, instruction format 700 described and illustrated are macro-instructions, in that they are instructions supplied to the execution unit, as opposed to micro-operations resulting from instruction decode once the instruction is processed.

In some embodiments, the graphics processor execution units natively support instructions in a 128-bit instruction format 710. A 64-bit compacted instruction format 730 is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted in the 64-bit format 730. The native instructions available in the 64-bit format 730 vary by embodiment. In some embodiments, the instruction is compacted in part using a set of index values in an index field 713. The execution unit hardware references a set of compaction tables based on the index values and uses the compaction table outputs to reconstruct a native instruction in the 128-bit instruction format 710. Other sizes and formats of instruction can be used.

For each format, instruction opcode 712 defines the operation that the execution unit is to perform. The execution units execute each instruction in parallel across the multiple data elements of each operand. For example, in response to an add instruction the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit performs each instruction across all data channels of the operands. In some embodiments, instruction control field 714 enables control over certain execution options, such as channels selection (e.g., predication) and data channel order (e.g., swizzle). For instructions in the 128-bit instruction format 710 an exec-size field 716 limits the number of data channels that will be executed in parallel. In some embodiments, exec-size field 716 is not available for use in the 64-bit compact instruction format 730.

Some execution unit instructions have up to three operands including two source operands, src0 720, src1 722, and one destination 718. In some embodiments, the execution units support dual destination instructions, where one of the destinations is implied. Data manipulation instructions can have a third source operand (e.g., SRC2 724), where the instruction opcode 712 determines the number of source operands. An instruction's last source operand can be an immediate (e.g., hard-coded) value passed with the instruction.

In some embodiments, the 128-bit instruction format 710 includes an access/address mode field 726 specifying, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is directly provided by bits in the instruction.

In some embodiments, the 128-bit instruction format 710 includes an access/address mode field 726, which specifies an address mode and/or an access mode for the instruction. In one embodiment the access mode is used to define a data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands and when in a second mode, the instruction may use 16-byte-aligned addressing for all source and destination operands.

In one embodiment, the address mode portion of the access/address mode field 726 determines whether the instruction is to use direct or indirect addressing. When direct register addressing mode is used bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands may be computed based on an address register value and an address immediate field in the instruction.

In some embodiments instructions are grouped based on opcode 712 bit-fields to simplify Opcode decode 740. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely an example. In some embodiments, a move and logic opcode group 742 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logic group 742 shares the five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxxb. A flow control instruction group 744 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). A miscellaneous instruction group 746 includes a mix of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instruction group 748 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 748 performs the arithmetic operations in parallel across data channels. The vector math group 750 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands. The illustrated opcode decode 740, in one embodiment, can be used to determine which portion of an execution unit will be used to execute a decoded instruction. For example, some instructions may be designated as systolic instructions that will be performed by a systolic array. Other instructions, such as ray-tracing instructions (not shown) can be routed to a ray-tracing core or ray-tracing logic within a slice or partition of execution logic.

Graphics Pipeline

FIG. 8 is a block diagram of another embodiment of a graphics processor 800. Elements of FIG. 8 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

In some embodiments, graphics processor 800 includes a geometry pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a render output pipeline 870. In some embodiments, graphics processor 800 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor 800 via a ring interconnect 802. In some embodiments, ring interconnect 802 couples graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 802 are interpreted by a command streamer 803, which supplies instructions to individual components of the geometry pipeline 820 or the media pipeline 830.

In some embodiments, command streamer 803 directs the operation of a vertex fetcher 805 that reads vertex data from memory and executes vertex-processing commands provided by command streamer 803. In some embodiments, vertex fetcher 805 provides vertex data to a vertex shader 807, which performs coordinate space transformation and lighting operations to each vertex. In some embodiments, vertex fetcher 805 and vertex shader 807 execute vertex-processing instructions by dispatching execution threads to execution units 852A-852B via a thread dispatcher 831.

In some embodiments, execution units 852A-852B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution units 852A-852B have an attached L1 cache 851 that is specific for each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

In some embodiments, geometry pipeline 820 includes tessellation components to perform hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 811 configures the tessellation operations. A programmable domain shader 817 provides back-end evaluation of tessellation output. A tessellator 813 operates at the direction of hull shader 811 and contains special purpose logic to generate a set of detailed geometric objects based on a coarse geometric model that is provided as input to geometry pipeline 820. In some embodiments, if tessellation is not used, tessellation components (e.g., hull shader 811, tessellator 813, and domain shader 817) can be bypassed.

In some embodiments, complete geometric objects can be processed by a geometry shader 819 via one or more threads dispatched to execution units 852A-852B, or can proceed directly to the clipper 829. In some embodiments, the geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as in previous stages of the graphics pipeline. If the tessellation is disabled, the geometry shader 819 receives input from the vertex shader 807. In some embodiments, geometry shader 819 is programmable by a geometry shader program to perform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper 829 processes vertex data. The clipper 829 may be a fixed function clipper or a programmable clipper having clipping and geometry shader functions. In some embodiments, a rasterizer and depth test component 873 in the render output pipeline 870 dispatches pixel shaders to convert the geometric objects into per pixel representations. In some embodiments, pixel shader logic is included in thread execution logic 850. In some embodiments, an application can bypass the rasterizer and depth test component 873 and access un-rasterized vertex data via a stream out unit 823.

The graphics processor 800 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and message passing amongst the major components of the processor. In some embodiments, execution units 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via a data port 856 to perform memory access and communicate with render output pipeline components of the processor. In some embodiments, sampler 854, caches 851, 858 and execution units 852A-852B each have separate memory access paths. In one embodiment the texture cache 858 can also be configured as a sampler cache.

In some embodiments, render output pipeline 870 contains a rasterizer and depth test component 873 that converts vertex-based objects into an associated pixel-based representation. In some embodiments, the rasterizer logic includes a windower/masker unit to perform fixed function triangle and line rasterization. An associated render cache 878 and depth cache 879 are also available in some embodiments. A pixel operations component 877 performs pixel-based operations on the data, though in some instances, pixel operations associated with 2D operations (e.g. bit block image transfers with blending) are performed by the 2D engine 841, or substituted at display time by the display controller 843 using overlay display planes. In some embodiments, a shared L3 cache 875 is available to all graphics components, allowing the sharing of data without the use of main system memory.

In some embodiments, graphics processor media pipeline 830 includes a media engine 837 and a video front-end 834. In some embodiments, video front-end 834 receives pipeline commands from the command streamer 803. In some embodiments, media pipeline 830 includes a separate command streamer. In some embodiments, video front-end 834 processes media commands before sending the command to the media engine 837. In some embodiments, media engine 837 includes thread spawning functionality to spawn threads for dispatch to thread execution logic 850 via thread dispatcher 831.

In some embodiments, graphics processor 800 includes a display engine 840. In some embodiments, display engine 840 is external to processor 800 and couples with the graphics processor via the ring interconnect 802, or some other interconnect bus or fabric. In some embodiments, display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, display engine 840 contains special purpose logic capable of operating independently of the 3D pipeline. In some embodiments, display controller 843 couples with a display device (not shown), which may be a system integrated display device, as in a laptop computer, or an external display device attached via a display device connector.

In some embodiments, the geometry pipeline 820 and media pipeline 830 are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls that are specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and/or Vulkan graphics and compute API, all from the Khronos Group. In some embodiments, support may also be provided for the Direct3D library from the Microsoft Corporation. In some embodiments, a combination of these libraries may be supported. Support may also be provided for the Open Source Computer Vision Library (OpenCV). A future API with a compatible 3D pipeline would also be supported if a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor.

Graphics Pipeline Programming

FIG. 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments. FIG. 9B is a block diagram illustrating a graphics processor command sequence 910 according to an embodiment. The solid lined boxes in FIG. 9A illustrate the components that are generally included in a graphics command while the dashed lines include components that are optional or that are only included in a sub-set of the graphics commands. The exemplary graphics processor command format 900 of FIG. 9A includes data fields to identify a client 902, a command operation code (opcode) 904, and data 906 for the command A sub-opcode 905 and a command size 908 are also included in some commands.

In some embodiments, client 902 specifies the client unit of the graphics device that processes the command data. In some embodiments, a graphics processor command parser examines the client field of each command to condition the further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a render unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the commands Once the command is received by the client unit, the client unit reads the opcode 904 and, if present, sub-opcode 905 to determine the operation to perform. The client unit performs the command using information in data field 906. For some commands an explicit command size 908 is expected to specify the size of the command In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments commands are aligned via multiples of a double word. Other command formats can be used.

The flow diagram in FIG. 9B illustrates an exemplary graphics processor command sequence 910. In some embodiments, software or firmware of a data processing system that features an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. A sample command sequence is shown and described for purposes of example only as embodiments are not limited to these specific commands or to this command sequence. Moreover, the commands may be issued as batch of commands in a command sequence, such that the graphics processor will process the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence 910 may begin with a pipeline flush command 912 to cause any active graphics pipeline to complete the currently pending commands for the pipeline. In some embodiments, the 3D pipeline 922 and the media pipeline 924 do not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands In response to a pipeline flush, the command parser for the graphics processor will pause command processing until the active drawing engines complete pending operations and the relevant read caches are invalidated. Optionally, any data in the render cache that is marked ‘dirty’ can be flushed to memory. In some embodiments, pipeline flush command 912 can be used for pipeline synchronization or before placing the graphics processor into a low power state.

In some embodiments, a pipeline select command 913 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, a pipeline select command 913 is required only once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command 912 is required immediately before a pipeline switch via the pipeline select command 913.

In some embodiments, a pipeline control command 914 configures a graphics pipeline for operation and is used to program the 3D pipeline 922 and the media pipeline 924. In some embodiments, pipeline control command 914 configures the pipeline state for the active pipeline. In one embodiment, the pipeline control command 914 is used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands.

In some embodiments, return buffer state commands 916 are used to configure a set of return buffers for the respective pipelines to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and to perform cross thread communication. In some embodiments, the return buffer state 916 includes selecting the size and number of return buffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on the active pipeline for operations. Based on a pipeline determination 920, the command sequence is tailored to the 3D pipeline 922 beginning with the 3D pipeline state 930 or the media pipeline 924 beginning at the media pipeline state 940.

The commands to configure the 3D pipeline state 930 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are to be configured before 3D primitive commands are processed. The values of these commands are determined at least in part based on the particular 3D API in use. In some embodiments, 3D pipeline state 930 commands are also able to selectively disable or bypass certain pipeline elements if those elements will not be used.

In some embodiments, 3D primitive 932 command is used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters that are passed to the graphics processor via the 3D primitive 932 command are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 932 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, 3D primitive 932 command is used to perform vertex operations on 3D primitives via vertex shaders. To process vertex shaders, 3D pipeline 922 dispatches shader execution threads to graphics processor execution units.

In some embodiments, 3D pipeline 922 is triggered via an execute 934 command or event. In some embodiments, a register write triggers command execution. In some embodiments execution is triggered via a ‘go’ or ‘kick’ command in the command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel back end operations may also be included for those operations.

In some embodiments, the graphics processor command sequence 910 follows the media pipeline 924 path when performing media operations. In general, the specific use and manner of programming for the media pipeline 924 depends on the media or compute operations to be performed. Specific media decode operations may be offloaded to the media pipeline during media decode. In some embodiments, the media pipeline can also be bypassed and media decode can be performed in whole or in part using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to the rendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similar manner as the 3D pipeline 922. A set of commands to configure the media pipeline state 940 are dispatched or placed into a command queue before the media object commands 942. In some embodiments, commands for the media pipeline state 940 include data to configure the media pipeline elements that will be used to process the media objects. This includes data to configure the video decode and video encode logic within the media pipeline, such as encode or decode format. In some embodiments, commands for the media pipeline state 940 also support the use of one or more pointers to “indirect” state elements that contain a batch of state settings.

In some embodiments, media object commands 942 supply pointers to media objects for processing by the media pipeline. The media objects include memory buffers containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing a media object command 942. Once the pipeline state is configured and media object commands 942 are queued, the media pipeline 924 is triggered via an execute command 944 or an equivalent execute event (e.g., register write). Output from media pipeline 924 may then be post processed by operations provided by the 3D pipeline 922 or the media pipeline 924. In some embodiments, GPGPU operations are configured and executed in a similar manner as media operations.

Graphics Software Architecture

FIG. 10 illustrates an exemplary graphics software architecture for a data processing system 1000 according to some embodiments. In some embodiments, software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, processor 1030 includes a graphics processor 1032 and one or more general-purpose processor core(s) 1034. The graphics application 1010 and operating system 1020 each execute in the system memory 1050 of the data processing system.

In some embodiments, 3D graphics application 1010 contains one or more shader programs including shader instructions 1012. The shader language instructions may be in a high-level shader language, such as the High-Level Shader Language (HLSL) of Direct3D, the OpenGL Shader Language (GLSL), and so forth. The application also includes executable instructions 1014 in a machine language suitable for execution by the general-purpose processor core 1034. The application also includes graphics objects 1016 defined by vertex data.

In some embodiments, operating system 1020 is a Microsoft® Windows® operating system from the Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. The operating system 1020 can support a graphics API 1022 such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is in use, the operating system 1020 uses a front-end shader compiler 1024 to compile any shader instructions 1012 in HLSL into a lower-level shader language. The compilation may be a just-in-time (JIT) compilation or the application can perform shader pre-compilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 1010. In some embodiments, the shader instructions 1012 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

In some embodiments, user mode graphics driver 1026 contains a back-end shader compiler 1027 to convert the shader instructions 1012 into a hardware specific representation. When the OpenGL API is in use, shader instructions 1012 in the GLSL high-level language are passed to a user mode graphics driver 1026 for compilation. In some embodiments, user mode graphics driver 1026 uses operating system kernel mode functions 1028 to communicate with a kernel mode graphics driver 1029. In some embodiments, kernel mode graphics driver 1029 communicates with graphics processor 1032 to dispatch commands and instructions.

IP Core Implementations

One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium may include instructions which represent various logic within the processor. When read by a machine, the instructions may cause the machine to fabricate the logic to perform the techniques described herein. Such representations, known as “IP cores,” are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model on fabrication machines that manufacture the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.

FIG. 11A is a block diagram illustrating an IP core development system 1100 that may be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 1100 may be used to generate modular, re-usable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SOC integrated circuit). A design facility 1130 can generate a software simulation 1110 of an IP core design in a high-level programming language (e.g., C/C++). The software simulation 1110 can be used to design, test, and verify the behavior of the IP core using a simulation model 1112. The simulation model 1112 may include functional, behavioral, and/or timing simulations. A register transfer level (RTL) design 1115 can then be created or synthesized from the simulation model 1112. The RTL design 1115 is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including the associated logic performed using the modeled digital signals. In addition to an RTL design 1115, lower-level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the particular details of the initial design and simulation may vary.

The RTL design 1115 or equivalent may be further synthesized by the design facility into a hardware model 1120, which may be in a hardware description language (HDL), or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a 3rd party fabrication facility 1165 using non-volatile memory 1140 (e.g., hard disk, flash memory, or any non-volatile storage medium). Alternatively, the IP core design may be transmitted (e.g., via the Internet) over a wired connection 1150 or wireless connection 1160. The fabrication facility 1165 may then fabricate an integrated circuit that is based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

FIG. 11B illustrates a cross-section side view of an integrated circuit package assembly 1170, according to some embodiments described herein. The integrated circuit package assembly 1170 illustrates an implementation of one or more processor or accelerator devices as described herein. The package assembly 1170 includes multiple units of hardware logic 1172, 1174 connected to a substrate 1180. The logic 1172, 1174 may be implemented at least partly in configurable logic or fixed-functionality logic hardware, and can include one or more portions of any of the processor core(s), graphics processor(s), or other accelerator devices described herein. Each unit of logic 1172, 1174 can be implemented within a semiconductor die and coupled with the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180, and can include interconnects such as, but not limited to bumps or pillars. In some embodiments, the interconnect structure 1173 may be configured to route electrical signals such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the logic 1172, 1174. In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. The substrate 1180 may include other suitable types of substrates in other embodiments. The package assembly 1170 can be connected to other electrical devices via a package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, other chipset, or multi-chip module.

In some embodiments, the units of logic 1172, 1174 are electrically coupled with a bridge 1182 that is configured to route electrical signals between the logic 1172, 1174. The bridge 1182 may be a dense interconnect structure that provides a route for electrical signals. The bridge 1182 may include a bridge substrate composed of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide a chip-to-chip connection between the logic 1172, 1174.

Although two units of logic 1172, 1174 and a bridge 1182 are illustrated, embodiments described herein may include more or fewer logic units on one or more dies. The one or more dies may be connected by zero or more bridges, as the bridge 1182 may be excluded when the logic is included on a single die. Alternatively, multiple dies or units of logic can be connected by one or more bridges. Additionally, multiple logic units, dies, and bridges can be connected together in other possible configurations, including three-dimensional configurations.

FIG. 11C illustrates a package assembly 1190 that includes multiple units of hardware logic chiplets connected to a substrate 1180 (e.g., base die). A graphics processing unit, parallel processor, and/or compute accelerator as described herein can be composed from diverse silicon chiplets that are separately manufactured. In this context, a chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device. Additionally, the chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein enable the interconnection and communication between the different forms of IP within the GPU. IP cores can be manufactured using different process technologies and composed during manufacturing, which avoids the complexity of converging multiple IPs, especially on a large SoC with several flavors IPs, to the same manufacturing process. Enabling the use of multiple process technologies improves the time to market and provides a cost-effective way to create multiple product SKUs. Additionally, the disaggregated IPs are more amenable to being power gated independently, components that are not in use on a given workload can be powered off, reducing overall power consumption.

The hardware logic chiplets can include special purpose hardware logic chiplets 1172, logic or I/O chiplets 1174, and/or memory chiplets 1175. The hardware logic chiplets 1172 and logic or I/O chiplets 1174 may be implemented at least partly in configurable logic or fixed-functionality logic hardware and can include one or more portions of any of the processor core(s), graphics processor(s), parallel processors, or other accelerator devices described herein. The memory chiplets 1175 can be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory.

Each chiplet can be fabricated as separate semiconductor die and coupled with the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the various chiplets and logic within the substrate 1180. The interconnect structure 1173 can include interconnects such as, but not limited to bumps or pillars. In some embodiments, the interconnect structure 1173 may be configured to route electrical signals such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the logic, I/O and memory chiplets.

In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. The substrate 1180 may include other suitable types of substrates in other embodiments. The package assembly 1190 can be connected to other electrical devices via a package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, other chipset, or multi-chip module.

In some embodiments, a logic or I/O chiplet 1174 and a memory chiplet 1175 can be electrically coupled via a bridge 1187 that is configured to route electrical signals between the logic or I/O chiplet 1174 and a memory chiplet 1175. The bridge 1187 may be a dense interconnect structure that provides a route for electrical signals. The bridge 1187 may include a bridge substrate composed of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide a chip-to-chip connection between the logic or I/O chiplet 1174 and a memory chiplet 1175. The bridge 1187 may also be referred to as a silicon bridge or an interconnect bridge. For example, the bridge 1187, in some embodiments, is an Embedded Multi-die Interconnect Bridge (EMIB). In some embodiments, the bridge 1187 may simply be a direct connection from one chiplet to another chiplet.

The substrate 1180 can include hardware components for I/O 1191, cache memory 1192, and other hardware logic 1193. A fabric 1185 can be embedded in the substrate 1180 to enable communication between the various logic chiplets and the logic 1191, 1193 within the substrate 1180. In one embodiment, the I/O 1191, fabric 1185, cache, bridge, and other hardware logic 1193 can be integrated into a base die that is layered on top of the substrate 1180.

In various embodiments a package assembly 1190 can include fewer or greater number of components and chiplets that are interconnected by a fabric 1185 or one or more bridges 1187. The chiplets within the package assembly 1190 may be arranged in a 3D or 2.5D arrangement. In general, bridge structures 1187 may be used to facilitate a point to point interconnect between, for example, logic or I/O chiplets and memory chiplets. The fabric 1185 can be used to interconnect the various logic and/or I/O chiplets (e.g., chiplets 1172, 1174, 1191, 1193). with other logic and/or I/O chiplets. In one embodiment, the cache memory 1192 within the substrate can act as a global cache for the package assembly 1190, part of a distributed global cache, or as a dedicated cache for the fabric 1185.

FIG. 11D illustrates a package assembly 1194 including interchangeable chiplets 1195, according to an embodiment. The interchangeable chiplets 1195 can be assembled into standardized slots on one or more base chiplets 1196, 1198. The base chiplets 1196, 1198 can be coupled via a bridge interconnect 1197, which can be similar to the other bridge interconnects described herein and may be, for example, an EMIB. Memory chiplets can also be connected to logic or I/O chiplets via a bridge interconnect. I/O and logic chiplets can communicate via an interconnect fabric. The base chiplets can each support one or more slots in a standardized format for one of logic or I/O or memory/cache.

In one embodiment, SRAM and power delivery circuits can be fabricated into one or more of the base chiplets 1196, 1198, which can be fabricated using a different process technology relative to the interchangeable chiplets 1195 that are stacked on top of the base chiplets. For example, the base chiplets 1196, 1198 can be fabricated using a larger process technology, while the interchangeable chiplets can be manufactured using a smaller process technology. One or more of the interchangeable chiplets 1195 may be memory (e.g., DRAM) chiplets. Different memory densities can be selected for the package assembly 1194 based on the power, and/or performance targeted for the product that uses the package assembly 1194. Additionally, logic chiplets with a different number of type of functional units can be selected at time of assembly based on the power, and/or performance targeted for the product. Additionally, chiplets containing IP logic cores of differing types can be inserted into the interchangeable chiplet slots, enabling hybrid processor designs that can mix and match different technology IP blocks.

Exemplary System on a Chip Integrated Circuit

FIGS. 12 and 13A-13B illustrate exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included, including additional graphics processors/cores, peripheral interface controllers, or general-purpose processor cores.

FIG. 12 is a block diagram illustrating an exemplary system on a chip integrated circuit 1200 that may be fabricated using one or more IP cores, according to an embodiment. Exemplary integrated circuit 1200 includes one or more application processor(s) 1205 (e.g., CPUs), at least one graphics processor 1210, and may additionally include an image processor 1215 and/or a video processor 1220, any of which may be a modular IP core from the same or multiple different design facilities. Integrated circuit 1200 includes peripheral or bus logic including a USB controller 1225, UART controller 1230, an SPI/SDIO controller 1235, and an I2S/I2C controller 1240. Additionally, the integrated circuit can include a display device 1245 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1250 and a mobile industry processor interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 including flash memory and a flash memory controller. Memory interface may be provided via a memory controller 1265 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 1270.

FIGS. 13A-13B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 13A illustrates an exemplary graphics processor 1310 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. FIG. 13B illustrates an additional exemplary graphics processor 1340 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. Graphics processor 1310 of FIG. 13A is an example of a low power graphics processor core. Graphics processor 1340 of FIG. 13B is an example of a higher performance graphics processor core. Each of the graphics processors 1310, 1340 can be variants of the graphics processor 1210 of FIG. 12.

As shown in FIG. 13A, graphics processor 1310 includes a vertex processor 1305 and one or more fragment processor(s) 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D, through 1315N-1, and 1315N). Graphics processor 1310 can execute different shader programs via separate logic, such that the vertex processor 1305 is optimized to execute operations for vertex shader programs, while the one or more fragment processor(s) 1315A-1315N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 1305 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processor(s) 1315A-1315N use the primitive and vertex data generated by the vertex processor 1305 to produce a framebuffer that is displayed on a display device. In one embodiment, the fragment processor(s) 1315A-1315N are optimized to execute fragment shader programs as provided for in the OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in the Direct 3D API.

Graphics processor 1310 additionally includes one or more memory management units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s) 1330A-1330B. The one or more MMU(s) 1320A-1320B provide for virtual to physical address mapping for the graphics processor 1310, including for the vertex processor 1305 and/or fragment processor(s) 1315A-1315N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in the one or more cache(s) 1325A-1325B. In one embodiment the one or more MMU(s) 1320A-1320B may be synchronized with other MMUs within the system, including one or more MMUs associated with the one or more application processor(s) 1205, image processor 1215, and/or video processor 1220 of FIG. 12, such that each processor 1205-1220 can participate in a shared or unified virtual memory system. The one or more circuit interconnect(s) 1330A-1330B enable graphics processor 1310 to interface with other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection, according to embodiments.

As shown FIG. 13B, graphics processor 1340 includes the one or more MMU(s) 1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s) 1330A-1330B of the graphics processor 1310 of FIG. 13A. Graphics processor 1340 includes one or more shader core(s) 1355A-1355N (e.g., 1455A, 1355B, 1355C, 1355D, 1355E, 1355F, through 1355N-1, and 1355N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. The exact number of shader cores present can vary among embodiments and implementations.

Additionally, graphics processor 1340 includes an inter-core task manager 1345, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1355A-1355N and a tiling unit 1358 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.

Hierarchical Thread Scheduling

In some examples, hierarchical parallel thread execution can be applied whereby a single leading thread of a team of threads executes code while other worker threads wait to execute and process data generated by the leading thread. Writes to a team-shared local memory can be accessible by some or all threads in the team. Function calls can be dynamically linked, such that inside the function, a thread can access multiple threads' context. However, a branch into multiple threads' context may not occur without synchronization.

FIG. 14 depicts an example of execution of multiple teams of threads. In this example, completion of a leading thread T0 of teams 1402 and 1404 is followed by execution of a group of threads, T0 to Tn. Threads T1 to Tn can be considered idle worker threads until an inner parallel “for” loop permits multiple threads to run, which causes threads T1 to Tn to run. A group barrier can be executed to synchronize threads in the group after execution of multiple threads T0 to Tn and before execution of the single lead thread T0.

A barrier directive, signal or instruction can prevent processes from proceeding to the next line of code until the barrier is cleared. This allows a programmer to synchronize processes in the parallel program. An execution state can refer to a transition point from execution of a single leading thread in a group to execution of a group of threads. This forces a thread or work-item to wait until every other thread or work-item in the group reaches the barrier. When a barrier completes, the waiting threads are started, and the barrier can be reinitialized or cleared.

For example, a barrier directive can have the following format. barrier_id=0, op_type=p&c, fence_type=no_fence, where:

barrier_id represents a barrier identifier and is set to a single value of 0.

op_type of p&c can indicate a thread is to act as a producer and consumer of data.

fence_type=no fence can indicate memory sharing is not permitted.

FIG. 15 depicts an example of transition from a single leading thread to multiple worker threads. For example, a leading thread 1502 executes while waiting threads 1504 do not execute. After an inner parallel “for” loop requests or permits multiple threads to run, leading thread 1502 continues to run and worker threads 1506 execute but waiting threads 1508 do not execute. A group barrier directive is performed to synchronize worker threads 1506 with leading thread 1502 such that leading thread 1502 can become a consumer of data generated by worker threads 1506 (as well as leading thread 1502). After execution of the group barrier directive, merely leading thread 1502 executes and waiting threads 1510 do not execute.

The following depicts pseudo-code for the scenario of FIG. 15.

Teams: create and fork 8 teams Leading thread runs code in each team Put other 63 threads in sleep mode Parallel: Run leading thread and wake up 47 threads Run parallel for loop code with 48 threads End Parallel: Join Barrier for 48 active threads Leading thread continues to run Put 47 threads in sleep mode End Teams: Join

Some solutions can allow a single barrier per workgroup. However, large workgroup sizes with a single barrier may suffer a large synchronization cost from data duplication in shared local memory (SLM) and L1 caches, and can increase bandwidth usage to L3 caches. If smaller workgroups are chosen to reduce synchronization cost, but duplicate data in L1 cache and SLM and increases bandwidth usage to L3 cache.

Various embodiments enable use of multiple barriers per workgroup and an ability to define detailed producer-consumer patterns in a GPU sub-slice. Various embodiments provide a hardware signal_barrier extension to set an Instruction Pointer (IP) location at consumer point for parallel execution state transition from leading thread to a group of threads to efficiently enable hierarchical parallelism. Various embodiments add an extension to signal_barrier to request waiting threads to start executing from a given instruction pointer (IP) address in an instruction queue that can be used to support fork-join hierarchical parallelism on a GPU. Accordingly, workgroup size per sub-slice can be maximized, resulting in many benefits when used with a GPU or GPGPU architecture. In normalization fused deep learning training kernels, element-wise processing per thread can reduce a side-effect of going to large workgroup sizes because more threads perform co-operative preprocessing. Various embodiments of a signal barrier reduce a number of L3 cache reads and permit floating point unit (FPU) element-wise operations by enabling large workgroups at low synchronization cost.

Various advantages, but not required features, of some embodiments include: 1) reduction of thread synchronization overhead, 2) efficient usage of L1 cache and thus reduction of L3 cache bandwidth demand, and 3) reduction of element-wise pre-processing overhead (e.g., reduced power consumption by reducing computation).

Various embodiments allow a compiler to support more complex cases, specifically involving library function calls, or indirect function calls. Various embodiments can be used with at least A21, SPEC, Deep Learning, and High Performance Computing (HPC) applications. Various embodiments provide an extension instruction to C, C++, Fortran and DPC++ for hierarchical parallelism support.

For example, semantics of a signal barrier can be as follows:

signal_barrier(barrier_id, num_producers, num_consumers, op_type, fence_type, &L), where

barrier_id can indicate a barrier identifier number;

num_producers can indicate a number of threads producing data (e.g., “lead/master” thread);

num_consumers can indicate a number of threads waiting for data (e.g., waiting “worker” threads that consume data produced by producer);

op_type can indicate whether the signal barrier applies to a producer or consumer or both;

fence_type can indicate whether no fence or a memory fence is to be applied between producer data and the consumer; and

&L can indicate an instruction pointer (IP) to a position in an instruction buffer from which worker threads are to start execution.

In some examples, barrier_id can define up to 32 barrier identifiers per work group, although other numbers can be used such as 2, 4, 8, 16, 64, 128, and so forth.

A producer can be a producer of data that can be accessed by another thread. A consumer can be a thread that processes data generated by a producer or producer and consumer thread.

Field fence_type can refer to memory sharing between a producer and consumer such as SLM level or cache level (e.g., L1, L2, L3, LLC). If there is no memory sharing, produced data can be copied to a region of memory or cache that is accessible by the consumer.

Field &L can notify worker threads to start working from this instruction pointer (IP) location specified by a compiler in an instruction buffer after signal_barrier is released. If &L is null, then a next unexecuted instruction in an instruction buffer is executed by a thread that is subject to the signal_barrier.

Another instruction that can be used in various embodiments in conjunction with signal_barrier is wait_barrier(barrier_id). Instruction wait_barrier(barrier_id) stalls one or more threads subject to the signal_barrier until notification for release of barrier_id is received.

In some examples, a compiler can generate a signal_barrier for all threads (e.g., producer, consumer, or producer and consumer) and corresponding wait instructions that permit thread execution based on clearing of an associated signal_barrier. After reaching a signal barrier, one or more threads in a workgroup can issue a signal_barrier identifier to a hardware gateway device. The hardware gateway can count when all threads subject to a particular signal_barrier, as differentiated by a signal_barrier identifier, have signaled in order to release the barrier.

FIG. 16 depicts an example of use of multiple barriers. Along with an instruction to execute lead thread 1600, a compiler generates first signal barrier 1650 for lead thread 1600 and second signal barrier 1652 for waiting worker threads 1602. First signal barrier 1650 for lead thread 1600 can have the following format: signal_barrier(id, 1, 0, p_only, fence_slm, &L=null). Field id can indicate a barrier identifier for a particular work group that includes lead thread 1600 and waiting worker threads 1602. Signal barrier 1650 indicates lead thread 1600 is 1 producer thread that is producer only (p_only). Signal barrier 1650 indicates lead thread 1600 is not a consumer thread (e.g., zero (0) consumer threads). Field fence_slm indicates SLM can be shared between a producer thread and worker threads. The last field (&L=null) indicates a next instruction is to be executed after the barrier is lifted. When lead thread 1600 completes, a barrier identifier is provided to a gateway (not shown), the barrier is released, and worker threads 1602 can proceed to execute.

In some examples, second signal barrier 1652 is applied for waiting worker threads 1602. Second signal barrier 1652 can be of the following format: signal_barrier(id, 0, 63, c_only, fence_slm, &L=null). Field id can indicate a barrier identifier for a particular work group that includes lead thread 1600 and waiting worker threads 1602. In this example, in waiting worker threads 1602 there are 0 producer threads that are waiting and 63 waiting worker threads that are consumer only (c_only). Field fence_slm indicates SLM can be shared between a producer thread and worker threads. The last field (&L=null) indicates a next instruction is to be executed after the barrier is lifted.

Pseudo code for the flow of FIG. 16 to generate first and second signal barriers can be as follows.

if (tid != 0) { // tid is a thread identifier and tid=0 is lead thread 1600 signal_barrier(id, 0, 63, c_only, fence_slm, null) wait_barrier(id) } else { signal_barrier(id, 1, 0, p_only, fence_slm, null) }

In this example, the compiler issues third barrier 1654 with an instruction for execution of lead thread 1600 after completion of lead thread 1600 and executing worker threads 1604. Third barrier 1654 can have the following format: signal_barrier(0, 0, 0, 0, no_fence, null) to indicate there is no consumer thread waiting and the lead thread is not producer. In other words, there are no waiting threads for this particular execution of the lead thread. Field no_fence indicates there is no data sharing. However, third barrier 1654 need not be issued in some examples.

Various embodiments enable multiple hardware barriers per workgroup with flexibility of defining a thread in a workgroup that can be in one of three modes: producer only, consumer only or producer-consumer. A gateway unit can track producer and consumer completion counts per barrier identifier and send a notification to waiting threads without need for polling by threads for an indication of clearing of the signal barrier. However, polling can be applied by the waiting threads.

FIG. 17 depicts an example of use of a barrier gateway. A format of signal barrier that gateway 1702 implements can be of the following format: signal_barrier(id, 2, 2, p_and_c, fence_slm, null). In this example, thread group 1704 includes two producer threads and two consumer threads. Producer threads fill up a scratch buffer in shared local memory (SLM) or L1 cache and signal to a particular barrier number (id) in gateway 1702. Consumer threads signal to gateway 1702 of availability to consume data by issuing a particular barrier number (id) in gateway 1702.

Gateway 1702 can receive indications that a producer thread has completed with an indication of a barrier number (e.g., msg_signal_barrier (barrier_number)) and receive indications that a consumer thread is ready to consume data with an indication of a barrier number (e.g., msg_signal_barrier (barrier_number)). In this example, gateway 1702 is configured to implement a barrier that is to permit consumer threads to proceed after two producer threads indicate completion and two consumer threads indicate readiness to consume data. Gateway 1702 can issue eu_wait_barrier (barrier_number) to both consumer threads, or does not in some examples. After gateway 1702 detects, for the same barrier identifier, four indications (e.g., msg_signal_barrier (barrier_number)), gateway 1702 issues a notification (e.g., notify_wait_done(barrier_number)) that consumer threads of thread group 1704 can proceed to consume data from a scratch buffer in SLM. Accordingly, gateway 1702 issues a response to waiting consumer threads to notify consumer threads that producer threads have finished execution, but does not have to in some examples.

FIG. 18 depicts an example of multiple thread execution on a matrix of values that can utilize multiple signal barrier identifiers in accordance with various embodiments. An 8×4 matrix-multiply workload is used as an example to multiply matrix tile A with matrix B. Matrix tile A can be stored in SLM and matrix B can be stored in L1 cache. In some cases, SLM is a software managed cache, and a GPU kernel explicitly populates SLM before reading data from it for compute. SLM can be populated co-operatively using threads in a workgroup.

In this example, 32 different threads in a workgroup are organized in a two dimensional manner whereby a thread is executed to perform computations on a particular coordinate in the 8×4 matrix. For example, for row 0, four threads with thread identifiers Tid=0 to 3 are used. For row 1, four threads with thread identifiers Tid=4 to 7 are used, and so forth.

In this workgroup, threads that are part of a same row share the same A tile for compute (e.g., Tid=0, 1, 2, 3) and threads part of same column share the same B tile for compute (e.g., Tid=0, 4, 8, 12, 16, 20, 24, 28). Because A tile is stored in SLM, each thread will load a portion of A tile from global memory space to SLM and synchronization among threads can occur to ensure SLM population is complete before consuming data for computation.

Pseudo Code for each thread can be as follows:

1) Read portion of A tile from global memory, write to SLM 2) Synchronize among threads a. signal_barrier b. wait 3) Read A tile from SLM 4) Read B tile from L1 5) Compute (A_tile, B_tile)

Using a legacy named barrier feature, synchronization in step 2) must occur for all threads in a workgroup (e.g., wait until all 32 threads fill up SLM), since only one barrier for an entire workgroup could be used. Synchronization can include each thread signaling to a hardware gateway unit of completion of filling up an SLM and waiting for return signal (wait_done) from the hardware unit. This return signal can be sent when all the workgroup threads have signaled completion.

In some examples, four smaller workgroups inside one Dual Sub-Slice (DSS) (e.g., with multiple EUs) tensor can be defined as follows.

WorkGroup0: WorkGroup1: M = 0 . . . 127, N = 0 . . . 127 M = 0 . . . 127, N = 128 . . . 255 Workgroup2: WorkGroup3: M = 128 . . . 255, N = 0 . . . 127 M = 128 . . . 255, N = 128 . . . 255 In this example, Workgroup0 will read input tiles from L3 and populate SLM for M=0 . . . 127, N=0 . . . 127; Workgroup1 will read input tiles from L3 and populate SLM for M=0 . . . 127, N=128 . . . 255; and so forth. Even though M tile is shared, both workgroups need to read the tile again and populate SLM separately, since SLM is exclusive per workgroup. Although there is data sharing across workgroups, data copy operations are duplicated in SLM.

According to various embodiments, SLM population can be set so that producer-consumer dependency is only among a row of threads so that for Tid=0 . . . 3, consumption depends only on production by Tid=0 . . . 3; for Tid=4 . . . 7, consumption depends only on production by Tid=4 . . . 7; and so forth. However, without use of signal barrier features in accordance with embodiments described herein, some implementations can wait for all threads in a workgroup to complete. Synchronization affects performance (e.g., up to 30% performance degradation with a single barrier for large workgroup). To lower synchronization cost, workgroup size can be reduced but this may result in data duplication in SLM and L1 caches, and also increased bandwidth to L3 cache.

Using a multiple identifier named barrier feature in accordance with various embodiments, barrier synchronization at a sub-workgroup level granularity can be performed. In some examples, named barriers can be initialized for all rows of a workgroup. The following provides pseudo code with use of a named barrier for each thread.

1) Read portion of A tile from global memory and write to SLM 2) Synchronize among threads For row_id 0 to 7: a. barrier_id = row_id of thread in workgroup b. num_producers = 4, num_consumers=4, barrier_mode = PRODUCER_CONSUMER c. signal_barrier ( barrier_id, num_producer, num_consumer, barrier_mode, null, null) d. Wait ( barrier_id ) 3) Read A tile from SLM 4) Read B tile from L1 5) Compute ( A_tile, B_tile )

During compiling, various embodiments can define barrier_id, number of producer threads part of this barrier_id and number of consumer threads part of this barrier_id. In this example, 4 threads per row of a workgroup can be executed, and each of them is both producer and consumer. With multiple barrier identifiers, synchronization can occur solely among dependent threads. Various embodiments can maximize the workgroup size for data reuse of data stored in SLM or L1 caches and thus reduce the bandwidth to higher cache hierarchies and memory.

Example gains from use of named barriers observed for an element-wise fused layer in a transformer training workload are given below.

Number of FPU element-wise Number of instructions Kernel Configuration Efficiency L3 reads executed 1) 8 threads/workgroup 78% 1331712 3987456 (WG), Legacy barrier 2) 32 threads/WG, legacy 84% 1070016 2420736 barrier (very high (1.2x (1.4x synchronization cost) reduction) reduction) 3) 32 threads/WG, 8 92% 1070016 2420736 named barriers per (1.2x (1.4x WG - fine-grained reduction) reduction) synchronization - low synchronization cost.

FIG. 19 depicts an example system. Computing platform 1900 can use one or more processors 1902, memory 1912, and graphics processing units (GPUs) 1920. Various connections can couple processors 1902, memory 1912, and GPUs 1920. For example, an interconnect, bus, fabric, or network can be used as a connection. Computing platform 1900 can be a composite platform formed from distributed compute resources. For example, any connection can be used such as: Ethernet (IEEE 802.3), remote direct memory access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Peripheral Component Interconnect express (PCIe), Intel QuickPath Interconnect (QPI), Intel Ultra Path Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Omnipath, Compute Express Link (CXL), HyperTransport, high-speed fabric, NVLink, Advanced Microcontroller Bus Architecture (AMBA) interconnect, OpenCAPI, Gen-Z, Cache Coherent Interconnect for Accelerators (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G, and variations thereof.

Processors 1902 can include any type of central processing unit (CPU), core, graphics processing unit (GPU), field programmable gate array (FPGA), or application specific integrated circuit (ASIC). Memory 1912 can be any type of volatile or non-volatile memory, including persistent memory and byte-addressable memory (e.g., Intel Optane). In some examples, processors 1902 can execute an operating system (OS) 1908, driver 1906, and applications 1904. In some examples, OS 1908 can be any of Linux®, Windows® Server, FreeBSD, Android®, MacOS®, iOS®, or any other operating system. OS 1908 can run within a virtualized execution environment or outside of a virtualized execution environment.

A virtualized execution environment (VEE) (not depicted) can include at least a virtual machine or a container. A virtual machine (VM) can be software that runs an operating system and one or more applications. A VM can be defined by specification, configuration files, virtual disk file, non-volatile random access memory (NVRAM) setting file, and the log file and is backed by the physical resources of a host computing platform. A VM can be an OS or application environment that is installed on software, which imitates dedicated hardware. The end user has the same experience on a virtual machine as they would have on dedicated hardware. Specialized software, called a hypervisor, emulates the PC client or server's CPU, memory, hard disk, network and other hardware resources completely, enabling virtual machines to share the resources. The hypervisor can emulate multiple virtual hardware platforms that are isolated from each other, allowing virtual machines to run Linux® and Windows® Server operating systems on the same underlying physical host.

A container can be a software package of applications, configurations and dependencies so the applications run reliably on one computing environment to another. Containers can share an operating system installed on the server platform and run as isolated processes. A container can be a software package that contains everything the software needs to run such as system tools, libraries, and settings.

Applications 1904 can be any type of application including a media streaming application (e.g., video or audio), virtual reality application (including headset and sound emitters), augmented reality application, video or audio conference application, video game application, image processing or editing application, or machine learning (ML) inference model. Applications 1904 can be programmed according to any programming language or using code compatible with one or more of: FORTRAN, C, C++, OpenMP, ANL, SPEC ACCEL OMP OpenGL, OpenCL, DirectX, Vulkan, Python, DPC++, TensorFlow, Metal, or any shader or machine learning language. Applications 1904 can be compatible with A21 Exascale platform (e.g., HACC, QMCPACK, LULESH). In some examples, an application can request retrieval or storage of data, processing of data (e.g., hierarchical parallelism), training of machine learning models, inferences using machine learning models, or generation of image data (e.g., frame or display size worth of pixels) using platform resources such as processors 1902, memory 1912 and GPU 1920.

Driver 1906 can compile code to generate assembly language and assign signal barriers to threads to perform hierarchical parallel operations in accordance with various embodiments. For example, a thread can include a series of instructions executed consecutively. For example, driver 1906 can associate a signal barrier with any thread. For example, when a producer thread completes, the producer thread can issue a signal barrier identifier to gateway 1924. After all producer threads for a particular barrier identifier have completed, gateway 1924 can release a barrier for consumer threads that are waiting for completion of a producer thread associated with the particular barrier identifier. Other examples of releasing or clearing a barrier are described herein.

In some examples, driver 1906 can compile commands or APIs into hardware commands that can be processed directly by a GPU's command streamer. Various embodiments simplify control-flow of code generated by the compiler and reduce branch divergency on the code in GPU 1920. Various embodiments remove or reduce complexity of building software-based state machine with the hardware support for efficiently hierarchical parallelism support on GPU 1920. A command stream can trigger shader code instruction execution on EUs 1928. The code that executes on EUs 1928 can be compiled by a usermode driver's shader compiler component by compiling high level shading language (e.g., HLSL or dxasm) into ISA. In accordance with various embodiments, driver 1906 can compile shading language APIs by assigning compiled versions of APIs to a workgroup for execution using one or more threads and provide a signal barrier for one or more threads in a workgroup. Various examples of use of signal barriers are described herein. Various embodiments enable use of multiple barriers per workgroup with flexibility of defining a thread in a workgroup as producer only, consumer only or producer-consumer and can be associated with multiple barriers simultaneously.

Instruction fetch and decode 1922 can fetch and decode instructions from an instruction queue at specific instruction pointer locations that can specify operations of GPU 1920. For example, for instructions subject to a signal barrier but cleared of the signal barrier, gateway 1924 can permit scheduling of execution of those instructions as a thread or threads. The instructions can cause GPU 1920 to schedule, via scheduler 1926, a set of operations to be performed via EUs or execution logic 1928. Scheduler unit 1926 can be implemented as a microcontroller or a low energy-per-instruction processing core capable of performing instructions loaded from a firmware module. EUs 1928 can include execution logic and execution units described herein. EUs 1928 can execute machine commands from an instruction queue in instruction fetch and decode 1922 that were generated by driver 1906. Registers 1930 can be used to store data for processing by one or more EUs 1928. Memory 1932 (e.g., shared local memory (SLM) and cache 1934 (e.g., level 1, level 2 or level 3 cache) can be volatile or non-volatile memory devices used to store data before and/or after processing by EUs 1928. An SLM can be accessible by threads in a workgroup for collaborative processing.

Image data or other generated data (e.g., inference data) generated by EUs 1928 can be stored in generated data 1916 of memory 1912. A format of data can be floating point (FP) 8 bits, FP16, FP32, FP64, or any floating point with number of bits that are multiple of 2, or integer (int) 8 bit, integer 16, integer 32, or any integer with number of bits that are multiple of 2. Image data can be represented as pixels and of any image or video format.

FIG. 20 depicts an example process. The process can be performed by a driver or compiler that compiles shader instructions or APIs for execution on a GPU, GPGPU, or other processing system as one or more threads in a work group. At 2002, a code segment can be received for compiling. In some examples, the code segment includes a portion that uses hierarchical parallelism or a model where a leading thread of a team of threads executes code while other threads wait to execute and process data generated by the leading thread or threads.

At 2004, the code segment is compiled. For example, a portion of the code segment that applies hierarchical parallelism can be compiled and one or more signal barriers can be provided for a workgroup for producer or consumer threads and the one or more signal barriers can use one or more signal barrier identifiers for different threads. For example, a signal barrier can include a signal barrier identifier. The signal barrier identifier can be associated with a workgroup of one or more consumer and/or producer threads. In some embodiments, the signal barrier can identify whether a thread is a producer or consumer of data or both producer of data and consumer of data as well as number of producers or consumers. In some embodiments, the signal barrier can indicate a level of memory sharing among a producer thread and one or more waiting consumer threads. The signal barrier can indicate an instruction pointer location in an instruction queue to jump to after clearing of the signal barrier. For example, semantics of a signal barrier can be as follows:

signal_barrier(barrier_id, num_producers, num_consumers, op_type, fence_type, &L), as described herein.

FIG. 21 depicts an example process that can be performed by a computing system. For example, the computing system can include a GPU, GPGPU, CPU, or any type of processor. At 2102, the computing system executes an instruction in an instruction queue. For example, the instructions can cause execution of instruction threads according to hierarchical parallelism and include one or more signal barriers that include one or more signal barrier identifiers. At 2104, for completion of execution of any thread, a corresponding signal barrier identifier is identified. The thread can be a producer or consumer or both producer and consumer thread. For example, a barrier identifier can be provided to a gateway that is configured to determine if a barrier can be cleared.

At 2106, a determination is made by the gateway if any barrier associated with a barrier identifier can be cleared. For example, based on a count of received barrier identifiers meeting a number of producers, consumers, and/or producers and consumers identified in a signal barrier for the barrier identifier, the gateway can clear the signal barrier. Other examples of clearing a signal barrier are described herein. Based on a determination a barrier cannot be cleared, the process can repeat 2106 to determine if the barrier is cleared. Based on a determination a barrier can be cleared, the process can proceed to 2108.

At 2108, one or more waiting threads associated with the cleared barrier identity can be permitted to execute. For example, a gateway can clear a barrier by issuing a wait completed indicator to any waiting consumer thread or producer-consumer thread associated with the cleared barrier identity.

Dual Direction Signal Barrier

FIG. 22 depicts an example sequence using signal barriers. For example, producer and consumer threads can access a shared buffer in memory. A producer can write or copy content to the buffer and inform the consumer thread through the signal barrier that data is ready to be processed from the buffer. After a consumer processes content from the buffer, the consumer can inform the producer that the buffer is free to be written-to. Accordingly, two sets of barriers can be used: a barrier (Barrier_0) between a producer and consumer and a barrier (Barrier_1) between a consumer and a producer. In a manner described earlier, Barrier_0 can be initialized by threads with #Producers=P, #Consumers=C. In a manner described earlier, Barrier_1 can be initialized by threads with #Producers=C, #Consumers=P.

At 2250, one or more consumer threads indicate that they are ready to consume data from a buffer using signal barrier_0 but wait for all producer threads (P) to indicate data is ready to consume from the buffer using signal barrier_0. At 2202, one or more producer threads fill a buffer for consumption and a gateway clears signal barrier_0 to indicate that the buffer is ready for the consumer threads.

At 2204, one or more producer threads indicate that they are ready to produce a next set of data to write to the buffer using signal barrier_1 and wait for all consumer threads (C) to indicate the buffer is consumed using signal barrier_1. At 2252, one or more consumer threads consume data from the buffer and a gateway clears signal barrier_1 to indicate that consumption is complete and one or more producer threads can write to the buffer. In response to clearing of signal barrier_1, the one or more producer threads can write to the buffer.

At 2254, one or more consumer threads indicate that they are ready to consume content from a buffer using signal barrier_0 but wait for all producer threads (P) to indicate data is ready to consume from the buffer using signal barrier_0. At 2206, one or more producer threads fill the buffer for consumption and a gateway clears signal barrier_0. In response to clearing of signal barrier_0, one or more consumer threads consume data from the buffer.

Accordingly, two sets of named barrier can be used for full duplex communication between producers and consumers. Barrier_0 can be used for forward direction (e.g., producer fills buffer and informs consumer), whereas Barrier_1 can be used for backward direction (e.g., consumer empties buffer and informs producer that the buffer is free for use). However, in some systems, a number of active or in-flight barriers is a limited resource. For example, a gateway can only manage a limited number of in-flight barriers. Various embodiments provide a dual directional signal barrier that uses a single barrier for forward and backward communication from producer to consumer and consumer to producer. Accordingly, for dual directional barrier signaling from producer to consumer and consumer to producer, a single in-flight barrier can be used instead of two in-flight barriers.

In some examples, a format of some examples of a Dual Directional Named Barrier can be as follows.

signal_barrier(barrier_id, num_producers, num_consumers, op_type, mode, fence_type, &L), where

barrier_id can indicate a barrier identifier number;

num_producers can indicate a number of threads producing data (e.g., “lead/master” thread);

num_consumers can indicate a number of threads waiting for data (e.g., waiting “worker” threads that consume data produced by producer);

op_type can indicate whether the signal barrier applies to a producer or consumer or both;

mode can indicate a forward (FWD) or backward (BWD) mode of communication;

fence_type can indicate whether no fence or a memory fence is to be applied between producer data and the consumer; and

&L can indicate an instruction pointer (IP) to a position in an instruction buffer from which worker threads are to start execution.

Field barrier_id can define up to 32 barrier identifiers per work group, although other numbers can be used such as 2, 4, 8, 16, 64, 128, and so forth.

A producer can be a producer of data that can be accessed by another thread. A consumer can be a thread that processes data generated by a producer or producer and consumer thread.

Field mode can indicate a communication is forwards (FWD) or backwards (BWD). For example, for a barrier_id value and mode of FWD, data production is indicated whereby one or more consumers request one or more producers to produce data into a buffer or one or more producers indicate data is ready for consumption from a buffer. Note that the buffer can be a region of memory that is accessible to both the one or more producers and one or more consumers. For example, for a barrier_id value and mode of BWD, one or more producers can indicate to one or more consumers that they are ready to produce data to a buffer or one or more consumers can indicate to one or more producers that a buffer was consumed and the buffer is available to be written-to.

Field fence_type can refer to memory sharing between a producer and consumer such as SLM level or cache level (e.g., L1, L2, L3, LLC). If there is no memory sharing, produced data can be copied to a region of memory or cache that is accessible by the consumer.

Field &L can notify worker threads to start working from this instruction pointer (IP) location specified by a compiler in an instruction buffer after dual directional signal_barrier is released. If &L is null, then a next unexecuted instruction in an instruction buffer is executed by a thread that is subject to the dual directional signal_barrier.

Referring again to FIG. 19, and specifically gateway 1924, one dual directional barrier can be used between one or more producer threads and one or more consumer threads to identify when a barrier is to be cleared. In some examples, a dual directional barrier can be initialized by a thread, with one or more fields described earlier, including number of producers, number of consumers, and mode of communication (e.g., FWD or BWD). By configuring the dual directional barrier with a number of consumers and number of producers that are subject to the dual directional barrier as well as an op_type that indicates whether the dual directional barrier applies to a producer or consumer or both, gateway 1924 can determine when to clear the dual directional barrier.

For example, after completion of one or more instructions that are subject to a dual directional barrier, a producer thread can issue a message with the dual directional barrier identifier (barrier_id) and mode (e.g., FWD or BWD) to gateway 1924. Likewise, after completion of one or more instructions that are subject to a dual directional barrier, a consumer thread can issue a message with a dual directional signal barrier identifier and mode (e.g., FWD or BWD). Gateway 1924 can track a number of producers that issued a message with the same barrier ID and same mode and also track a number of consumers that issued a message with the same barrier ID and same mode and when the number of producers and number of consumers (e.g., fields num_producers and num_consumers) identified for a signal barrier identifier for the same mode are reached, gateway 1924 can release the dual directional barrier and allow the waiting thread (one or more consumers or one or more producers) to proceed.

For example, when a producer thread completes a processing (e.g., fills a buffer) that is subject to a dual directional signal barrier, the producer thread can issue a message with a signal barrier identifier with mode FWD to gateway 1924. After all producer threads have issued a particular dual directional barrier identifier and mode FWD, gateway 1924 can release the barrier for one or more consumer threads that are waiting for completion of one or more producer threads associated with the particular barrier identifier in order to proceed to processing content of the buffer.

For example, when a consumer thread requests one or more producers to produce data into a buffer that is subject to a dual directional signal barrier, the consumer thread can issue a message with a signal barrier identifier with mode FWD to gateway 1924. After all consumer threads have issued a particular dual directional barrier identifier and mode FWD, gateway 1924 can release the barrier for one or more producer threads that are waiting for completion of one or more consumer threads associated with the particular barrier identifier and the producer threads can proceed to filling the buffer with data.

For example, when a producer thread indicates it is ready to produce data to a buffer and requests use of a buffer, the producer thread can issue a message with a signal barrier identifier with mode BWD to gateway 1924. After all consumer threads for a particular dual directional barrier identifier have completed and indicated mode BWD, gateway 1924 can release the barrier for one or more producer threads that are waiting for release of the barrier associated with the particular barrier identifier and the producer threads can proceed to write data to the buffer.

Note that a mixture of one or more single direction signal barriers (e.g., as described with respect to FIG. 22) and one or more dual directional signal barriers, but with different barrier identifiers, can be registered with gateway 1924. In some cases, merely dual directional signal barriers are registered with gateway 1924.

FIG. 23 depicts an example sequence using a single dual directional signal barrier. At 2350, one or more consumer threads message signal barrier_0 in forward mode (FWD) to a gateway to indicate that one or more consumers are ready to process data from a buffer but wait in FWD mode for all producer threads (P) to message to signal barrier_0 in FWD mode. At 2302, one or more producer threads fill a buffer for consumption and message signal barrier_0 and FWD mode to the gateway to indicate that buffer is ready for consumption. Note that 2350 and 2302 can occur at the same or overlapping times, or different times.

In response to clearing of signal barrier_0 by the gateway, at 2352, one or more consumer threads consume data from the buffer and message signal barrier_0 in BWD mode to the gateway that buffer consumption is complete. At 2304, one or more producer threads message the gateway with signal barrier_0 in backward (BWD) mode that they are ready to produce a next set of data and wait in BWD mode for all consumer threads (C) to message the gateway with signal barrier_0 in BWD mode. Note that 2352 and 2304 can occur at the same or overlapping times, or different times.

At 2354, one or more consumer threads message signal barrier_0 to the gateway in FWD mode that they are ready to consume content from a buffer and wait in FWD mode for one or more producer threads to message signal barrier_0 in FWD mode to the gateway. In response to the gateway clearing signal barrier_0, at 2306, one or more producer threads fill a buffer for consumption and message signal barrier_0 in FWD mode to the gateway that the buffer is ready for consumption. In response to clearing of signal barrier_0 in FWD mode, one or more consumer threads consume data from the buffer. Note that 2354 and 2306 can occur at the same or overlapping times, or different times.

FIG. 24 depicts an example process. The process can be performed by a driver or compiler that compiles shader instructions or APIs for execution on a GPU, GPGPU, Accelerated Processing Unit (APU) or other processing system as one or more threads in a work group. At 2402, a code segment can be received for compiling. In some examples, the code segment includes a portion that uses hierarchical parallelism or a model where a leading thread of a team of threads executes code while other threads wait to execute and process data generated by the leading thread or threads.

At 2404, the code segment is compiled. For example, a portion of the code segment that applies hierarchical parallelism can be compiled and one or more signal barriers can be provided for a workgroup for producer or consumer threads and the one or more signal barriers can use one or more signal barrier identifiers for different threads. For example, a single direction signal barrier and/or dual directional signal barrier can be used. A dual directional signal barrier can include at least a signal barrier identifier and mode of operation. The signal barrier identifier can be associated with a workgroup of one or more consumer and/or producer threads. In some embodiments, the dual directional signal barrier can identify whether a thread is a producer or consumer of data or both producer of data and consumer of data as well as number of producers or consumers. In some embodiments, the mode can indicate a forward (FWD) or backward (BWD) mode of communication as described herein. In some embodiments, the dual directional signal barrier can indicate a level of memory sharing among a producer thread and one or more waiting consumer threads. The dual directional signal barrier can indicate an instruction pointer location in an instruction queue to jump to after clearing of the signal barrier. For example, semantics of a signal barrier can be as follows:

-   -   signal_barrier(barrier_id, num_producers, num_consumers,         op_type, mode, fence_type, &L), as described herein.

FIG. 25 depicts an example process that can be performed by a computing system. For example, the computing system can include a GPU, GPGPU, CPU, or any type of processor. At 2502, the computing system executes an instruction in an instruction queue. For example, the instructions can cause execution of instruction threads according to hierarchical parallelism and include one or more signal barriers that include one or more signal barrier identifiers and mode of operation (e.g., forward or backward). At 2504, for completion of execution of any thread, a corresponding signal barrier identifier is identified. The signal barrier can be a single direction signal barrier or dual directional signal barrier. The thread can be a producer or consumer or both producer and consumer thread. For example, a barrier identifier can be provided to a gateway that is configured to determine if a barrier can be cleared. A signal barrier mode can indicate whether a communication is forwards (FWD) or backwards (BWD). Note, as described herein, that a barrier can be associated with both modes (FWD and BWD), which is tracked by a gateway.

At 2506, a determination can made by the gateway if any barrier associated with a barrier identifier can be cleared. For example, for a dual directional barrier, based on a count of received barrier identifiers meeting a number of producers identified in a signal barrier and with a same mode (FWD or BWD), the gateway can clear the signal barrier. For example, for a dual directional barrier, based on a count of received barrier identifiers meeting a number of consumers identified in a signal barrier and with a same mode (FWD or BWD), the gateway can clear the signal barrier. Other examples of clearing a signal barrier are described herein. Based on a determination a barrier cannot be cleared, the process can repeat 2506. Based on a determination a barrier can be cleared, the process can proceed to 2508.

At 2508, barrier clearance can be communicated. For example, a gateway can clear a barrier by issuing a wait completed indicator to any waiting consumer thread or producer-consumer thread associated with the cleared barrier identity. In some examples, if the barrier is a dual directional signal barrier, communication to a producer or consumer can occur based signal barrier identifier value and on whether the mode is forward or backward.

For example, for a barrier identifier value and mode of forward, clearance of the barrier can allow one or more producers to produce data into a buffer or one or more consumers to process data from a buffer. For example, for a barrier identifier value and mode of backward, clearance of the barrier can allow one or more producers to write data to a buffer. Other examples are described herein.

The appearances of the phrase “one example” or “an example” are not necessarily all referring to the same example or embodiment. Any aspect described herein can be combined with any other aspect or similar aspect described herein, regardless of whether the aspects are described with respect to the same figure or element.

Some examples may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms “connected” and/or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

The terms “first,” “second,” and the like, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The term “asserted” used herein with reference to a signal denote a state of the signal, in which the signal is active, and which can be achieved by applying any logic level either logic 0 or logic 1 to the signal. The terms “follow” or “after” can refer to immediately following or following after some other event or events. In flow diagrams, other sequences of steps may also be performed according to alternative embodiments. Furthermore, additional steps may be added or removed depending on the particular applications. Any combination of changes can be used and one of ordinary skill in the art with the benefit of this disclosure would understand the many variations, modifications, and alternative embodiments thereof.

Disjunctive language such as the phrase “at least one of X, Y, or Z,” unless specifically stated otherwise, is otherwise understood within the context as used in general to present that an item, term, etc., may be either X, Y, or Z, or any combination thereof (e.g., X, Y, and/or Z). Thus, such disjunctive language is not generally intended to, and should not, imply that certain embodiments require at least one of X, at least one of Y, or at least one of Z to each be present. Additionally, conjunctive language such as the phrase “at least one of X, Y, and Z,” unless specifically stated otherwise, should also be understood to mean X, Y, Z, or any combination thereof, including “X, Y, and/or Z.’”

Embodiments of the invention may include various steps, which have been described above. The steps may be embodied in machine-executable instructions which may be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, these steps may be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

As described herein, instructions may refer to specific configurations of hardware such as application specific integrated circuits (ASICs) configured to perform certain operations or having a predetermined functionality or software instructions stored in memory embodied in a non-transitory computer readable medium. Thus, the techniques shown in the figures can be implemented using code and data stored and executed on one or more electronic devices (e.g., an end station, a network element, etc.). Such electronic devices store and communicate (internally and/or with other electronic devices over a network) code and data using computer machine-readable media, such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks; random access memory; read only memory; flash memory devices; phase-change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustical or other form of propagated signals—such as carrier waves, infrared signals, digital signals, etc.).

In addition, such electronic devices typically include a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input/output devices (e.g., a keyboard, a touchscreen, and/or a display), and network connections. The coupling of the set of processors and other components is typically through one or more busses and bridges (also termed as bus controllers). The storage device and signals carrying the network traffic respectively represent one or more machine-readable storage media and machine-readable communication media. Thus, the storage device of a given electronic device typically stores code and/or data for execution on the set of one or more processors of that electronic device. Of course, one or more parts of an embodiment of the invention may be implemented using different combinations of software, firmware, and/or hardware. Throughout this detailed description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without some of these specific details. In certain instances, well known structures and functions were not described in elaborate detail in order to avoid obscuring the subject matter of the present invention. Accordingly, the scope and spirit of the invention should be judged in terms of the claims which follow.

Example 1 includes a graphics processing apparatus comprising: a memory device and a graphics processing unit (GPU) coupled to the memory device, the GPU configured to: execute an instruction thread; determine if a dual directional signal barrier is associated with the instruction thread; and based on clearance of the dual directional signal barrier for a particular signal barrier identifier and a mode of operation, indicate a clearance of the dual directional signal barrier for the mode of operation, wherein the dual directional signal barrier is to provide a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.

Example 2 includes any example, and includes a gateway to receive indications of a dual directional signal barrier identifier and mode of operation and to selectively clear the dual directional signal barrier for the mode for a waiting instruction thread associated with the dual directional signal barrier identifier based on clearance conditions associated with the dual directional signal barrier being met.

Example 3 includes any example, wherein the clearance conditions comprise one or more of: a number of producer threads being completed for the mode of operation or a number of consumer threads being completed for the mode of operation.

Example 4 includes any example, wherein the gateway is to permit scheduling of execution of the waiting instruction thread based on clearance of the dual directional signal barrier for the waiting instruction thread.

Example 5 includes any example, wherein the dual directional signal barrier identifier is to identify one of multiple signal barriers.

Example 6 includes any example, wherein the dual directional signal barrier is to identify one or more of: a number of producer threads subject to the dual directional signal barrier, a number of consumer threads subject to the signal barrier, whether the dual directional signal barrier applies to consumer or producer type threads, the mode of operation, a memory sharing scheme, or an instruction pointer to an instruction queue.

Example 7 includes any example, wherein the mode of operation is to indicate a forward mode communication or a backwards communication, the forward communication is to indicate a request to produce data into a buffer or indicate data is ready for consumption from a buffer, and the backwards communication is to indicate a readiness to write data to a buffer or one or a buffer is available to be written-to.

Example 8 includes any example, wherein the GPU is configured to perform a hierarchical parallel thread execution using the dual directional signal barrier.

Example 9 includes any example, and includes a central processing unit (CPU) to generate compiled instructions that comprise an instruction performed by the instruction thread, the dual directional signal barrier, and a second instruction for execution by a waiting instruction thread.

Example 10 includes any example, and includes one or more of: a display to display content generated using the instruction thread, a network interface to receive content to be processed, and storage to store content generated using the instruction thread.

Example 11 includes any example, and includes a non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: execute a driver to: translate commands into processor executable instructions and based on a code segment including instructions of a hierarchical parallel order, provide a dual directional signal barrier, wherein the dual directional signal barrier comprises a signal barrier identifier that is selected from a plurality of identifiers, the dual directional signal barrier indicates a mode of operation and the dual directional signal barrier provides a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.

Example 12 includes any example, wherein the commands are compatible with one or more of: FORTRAN, C, C++, OpenMP, ANL, SPEC ACCEL OMP OpenGL, OpenCL, DirectX, Vulkan, Python, DPC++, TensorFlow, or Metal.

Example 13 includes any example, wherein the dual directional signal barrier is to identify one or more of: a number of producer threads subject to the dual directional signal barrier, a number of consumer threads subject to the signal barrier, whether the dual directional signal barrier applies to consumer or producer type threads, the mode of operation, a memory sharing scheme, or an instruction pointer to an instruction queue.

Example 14 includes any example, wherein execution of the dual directional signal barrier is to cause a graphics processing unit (GPU) to: determine if the dual directional signal barrier having a signal barrier identifier and mode of operation is cleared and based on the dual directional signal barrier being cleared, permit any waiting instruction thread associated with the dual directional signal barrier identifier and the mode of operation to commence with execution.

Example 15 includes any example, and includes instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: provide an instruction to indicate a dual directional signal barrier identifier and mode of operation to a gateway, wherein the gateway is to clear the dual directional signal barrier for a waiting instruction thread associated with the dual directional signal barrier identifier based on clearance conditions associated with the dual directional signal barrier being met.

Example 16 includes any example, wherein the clearance conditions comprise one or more of: for a signal barrier identifier and mode of operation, a specified number of producer threads indicated as completed and for a signal barrier identifier and mode of operation, a specified number of consumer threads indicated as completed.

Example 17 includes any example, wherein: the mode of operation is to indicate a forward mode communication or a backwards communication, the forward communication is to indicate a request to produce data into a buffer or indicate data is ready for consumption from a buffer, and the backwards communication is to indicate a readiness to write data to a buffer or one or a buffer is available to be written-to.

Example 18 includes any example, and includes a computer-implemented method comprising: determining if a dual directional signal barrier is cleared and based on the dual directional signal barrier being cleared, permit any waiting thread associated with the signal barrier identifier to commence with execution, wherein: the dual directional signal barrier comprises a signal barrier identifier that is selected from a plurality of identifiers, the dual directional signal barrier indicates a mode of operation and the dual directional signal barrier provides a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.

Example 19 includes any example, and includes: receiving indications of the dual directional signal barrier identifier at a gateway and selectively clearing, at the gateway, a dual directional signal barrier for a waiting thread associated with the dual directional signal barrier identifier and the mode of operation based on clearance conditions associated with the dual directional signal barrier being met.

Example 20 includes any example, wherein the clearance conditions comprise one or more of: a number of producer threads being completed for a signal barrier identifier and mode of operation or a number of consumer threads being completed for a signal barrier identifier and mode of operation.

Example 21 includes any example, wherein the dual directional signal barrier comprises one or more of: a number of producer threads subject to the signal barrier, a number of consumer threads subject to the signal barrier, whether the signal barrier applies to consumer or producer type threads, the mode of communication of barrier completion, a memory sharing scheme, or an instruction pointer to an instruction queue. 

What is claimed is:
 1. A graphics processing apparatus comprising: a memory device and a graphics processing unit (GPU) coupled to the memory device, the GPU configured to: execute an instruction thread; determine if a dual directional signal barrier is associated with the instruction thread; and based on clearance of the dual directional signal barrier for a particular signal barrier identifier and a mode of operation, indicate a clearance of the dual directional signal barrier for the mode of operation, wherein the dual directional signal barrier is to provide a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.
 2. The graphics processing apparatus of claim 1, comprising: a gateway to receive indications of a dual directional signal barrier identifier and mode of operation and to selectively clear the dual directional signal barrier for the mode for a waiting instruction thread associated with the dual directional signal barrier identifier based on clearance conditions associated with the dual directional signal barrier being met.
 3. The graphics processing apparatus of claim 2, wherein the clearance conditions comprise one or more of: a number of producer threads being completed for the mode of operation or a number of consumer threads being completed for the mode of operation.
 4. The graphics processing apparatus of claim 2, wherein the gateway is to permit scheduling of execution of the waiting instruction thread based on clearance of the dual directional signal barrier for the waiting instruction thread.
 5. The graphics processing apparatus of claim 1, wherein the dual directional signal barrier identifier is to identify one of multiple signal barriers.
 6. The graphics processing apparatus of claim 1, wherein the dual directional signal barrier is to identify one or more of: a number of producer threads subject to the dual directional signal barrier, a number of consumer threads subject to the signal barrier, whether the dual directional signal barrier applies to consumer or producer type threads, the mode of operation, a memory sharing scheme, or an instruction pointer to an instruction queue.
 7. The graphics processing apparatus of claim 1, wherein the mode of operation is to indicate a forward mode communication or a backwards communication, the forward communication is to indicate a request to produce data into a buffer or indicate data is ready for consumption from a buffer, and the backwards communication is to indicate a readiness to write data to a buffer or one or a buffer is available to be written-to.
 8. The graphics processing apparatus of claim 1, wherein the GPU is configured to perform a hierarchical parallel thread execution using the dual directional signal barrier.
 9. The graphics processing apparatus of claim 1, comprising a central processing unit (CPU) to generate compiled instructions that comprise an instruction performed by the instruction thread, the dual directional signal barrier, and a second instruction for execution by a waiting instruction thread.
 10. The graphics processing apparatus of claim 1, comprising one or more of: a display to display content generated using the instruction thread, a network interface to receive content to be processed, and storage to store content generated using the instruction thread.
 11. A non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: execute a driver to: translate commands into processor executable instructions and based on a code segment including instructions of a hierarchical parallel order, provide a dual directional signal barrier, wherein the dual directional signal barrier comprises a signal barrier identifier that is selected from a plurality of identifiers, the dual directional signal barrier indicates a mode of operation and the dual directional signal barrier provides a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.
 12. The computer-readable medium of claim 11, wherein the commands are compatible with one or more of: FORTRAN, C, C++, OpenMP, ANL, SPEC ACCEL OMP OpenGL, OpenCL, DirectX, Vulkan, Python, DPC++, TensorFlow, or Metal.
 13. The computer-readable medium of claim 11, wherein the dual directional signal barrier is to identify one or more of: a number of producer threads subject to the dual directional signal barrier, a number of consumer threads subject to the signal barrier, whether the dual directional signal barrier applies to consumer or producer type threads, the mode of operation, a memory sharing scheme, or an instruction pointer to an instruction queue.
 14. The computer-readable medium of claim 11, wherein execution of the dual directional signal barrier is to cause a graphics processing unit (GPU) to: determine if the dual directional signal barrier having a signal barrier identifier and mode of operation is cleared and based on the dual directional signal barrier being cleared, permit any waiting instruction thread associated with the dual directional signal barrier identifier and the mode of operation to commence with execution.
 15. The computer-readable medium of claim 11, comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: provide an instruction to indicate a dual directional signal barrier identifier and mode of operation to a gateway, wherein the gateway is to clear the dual directional signal barrier for a waiting instruction thread associated with the dual directional signal barrier identifier based on clearance conditions associated with the dual directional signal barrier being met.
 16. The computer-readable medium of claim 15, wherein the clearance conditions comprise one or more of: for a signal barrier identifier and mode of operation, a specified number of producer threads indicated as completed and for a signal barrier identifier and mode of operation, a specified number of consumer threads indicated as completed.
 17. The computer-readable medium of claim 11, wherein: the mode of operation is to indicate a forward mode communication or a backwards communication, the forward communication is to indicate a request to produce data into a buffer or indicate data is ready for consumption from a buffer, and the backwards communication is to indicate a readiness to write data to a buffer or one or a buffer is available to be written-to.
 18. A computer-implemented method comprising: determining if a dual directional signal barrier is cleared and based on the dual directional signal barrier being cleared, permit any waiting thread associated with the signal barrier identifier to commence with execution, wherein: the dual directional signal barrier comprises a signal barrier identifier that is selected from a plurality of identifiers, the dual directional signal barrier indicates a mode of operation and the dual directional signal barrier provides a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.
 19. The method of claim 18, comprising: receiving indications of the dual directional signal barrier identifier at a gateway and selectively clearing, at the gateway, a dual directional signal barrier for a waiting thread associated with the dual directional signal barrier identifier and the mode of operation based on clearance conditions associated with the dual directional signal barrier being met.
 20. The method of claim 19, wherein the clearance conditions comprise one or more of: a number of producer threads being completed for a signal barrier identifier and mode of operation or a number of consumer threads being completed for a signal barrier identifier and mode of operation.
 21. The method of claim 18, wherein the dual directional signal barrier comprises one or more of: a number of producer threads subject to the signal barrier, a number of consumer threads subject to the signal barrier, whether the signal barrier applies to consumer or producer type threads, the mode of communication of barrier completion, a memory sharing scheme, or an instruction pointer to an instruction queue. 